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公开(公告)号：JPH0997128A
公开(公告)日：1997-04-08
申请号：JP24715295
申请日：1995-09-26
Applicant: IBM
Inventor： MATSUSHIMA SHINJI , KONO SEIICHI , NAKANO MASATAKE , SHIRAISHI YUICHI
Abstract: PROBLEM TO BE SOLVED: To provide a superior information processing system which can drop or stop the operation frequency of CPU at appropriate timing even while asynchronous communication is executed with a peripheral equipment. SOLUTION: This system includes a CPU 11 which can be operated at a regular mode and a power saving mode whose power consumption is lower than the regular mode, one or more peripheral equipments 17, 23, buses 12, 16 and 22 for making communication between the peripheral equipments 17, 23 and CPU 11, a bus cycle detection means for monitoring a bus cycle on the buses, a state judgment means for deciding the operation mode of the CPU 11 in a specified bus cycle detected by the bus cycle detection means and a signal generation means for transmitting a control signal for switching the operation mode based on a judgment result by the state judgment means to the CPU 11.
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公开(公告)号：JPH0287188A
公开(公告)日：1990-03-28
申请号：JP23850288
申请日：1988-09-22
Applicant: IBM JAPAN , DEIKUSHII KK
Inventor： SEKIYA KAZUO , SHIRAISHI YUICHI , ENDO JOICHI , IGARASHI TOYOAKI
Abstract: PURPOSE:To display an image plane consisting of an optional number of lines than the number of display liens of a display device at an optional vertical position on a display panel at all times by providing a means which generates a signal for varying and setting the number of blank feeding shift clock pulses, feeding lines with the blank feeding shift clock, and making no display in the blank feeding period. CONSTITUTION:A generation part 60 for a horizontal synchronizing signal as an interface signal to a matrix display device consists of a generating circuit 61 for the blank feeding shift clock, a generating circuit 62 for pulses of frequency which is an (n) times as high as a horizontal synchronizing signal, and a kick circuit 63 for the generating circuit 61. In this case, lines are fed on the display device by as many as the blank feeding shift clock pulses in the blank feeding period and no display is made throughout the period. For the purpose, this blank feeding period is so set that when the number of lines on the image plane is smaller than that of the display panel, parts of unnecessary lines at the upper and lower part of the display panel are fed in blank, thereby displaying the image plane in the center. Further, the image plane can easily be displayed at an optical desired vertical position.
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公开(公告)号：JPH0285889A
公开(公告)日：1990-03-27
申请号：JP23629088
申请日：1988-09-22
Applicant: IBM JAPAN
Inventor： SEKIYA KAZUO , SHIRAISHI YUICHI
Abstract: PURPOSE:To facilitate the conversion, and also, to hold sequence and magnitude of a relative luminance of M pieces of gradations by specifying a relation of K, M and N, in the case of converting arbitrary M pieces of gradations of a K gradation gray scale to an N gradation. CONSTITUTION:A gray scale converter is formed by a first table Tin and a second table Tout. The table Tin is a processing table for generating the table Tout, and mapped to an N gradation having sequence and magnitude of M pieces of gradation relative luminances in a K gradation. Subsequently, the contents of the table Tin are allowed to correspond to the K gradation, and mapped to the table Tout. In this case, when there is a condition of K>N>=M, the conversion corresponds to one-to-one and executed easily. Also, even when a CRT controller can use only an arbitrary N gradation in the K gradation, a display can be executed on a panel PDP.
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公开(公告)号：DE69630851D1
公开(公告)日：2004-01-08
申请号：DE69630851
申请日：1996-09-16
Applicant: IBM
Inventor： INUI TAKASHI , KAWANO SEIICHI , MATSUSHIMA SHINJI , NAKANO MASAYOSHI , SHIRAISHI YUICHI
IPC: G06F1/32
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公开(公告)号：DE69630851T2
公开(公告)日：2004-09-02
申请号：DE69630851
申请日：1996-09-16
Applicant: IBM
Inventor： INUI TAKASHI , KAWANO SEIICHI , MATSUSHIMA SHINJI , NAKANO MASAYOSHI , SHIRAISHI YUICHI
IPC: G06F1/32
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Patent Agency Ranking
公开(公告)号：GB2223149A
公开(公告)日：1990-03-28
申请号：GB8913015
申请日：1989-06-06
Applicant: IBM
Inventor： SEKIYA KAZUO , SHIRAISHI YUICHI
Abstract: A display system for converting first gray level signal of N bits (N is integer larger than or equal to 2) representing 2 gray levels to second gray level signal representing 2 gray levels (M is integer satisfying N>M>/=1) : said display system comprising: means for separating said first gray level signal of N bits into higher M bits and lower N-M bits; 2 tables each of which stores P x Q modification values satisfying P x Q >/= 2 ; means for selecting one of said tables by using said NM bits; means for adding said M bits and each of modification values of said selected table to generate P x Q second gray level signals; and means for supplying said second gray level signals to a display device of 2 gray levels.
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公开(公告)号：DE68921123T2
公开(公告)日：1995-08-10
申请号：DE68921123
申请日：1989-08-08
Applicant: IBM
Inventor： SEKIYA KAZUO , SHIRAISHI YUICHI
Abstract: A display system for converting first gray level signal of N bits (N is integer larger than or equal to 2) representing 2 gray levels to second gray level signal representing 2 gray levels (M is integer satisfying N>M>/=1) : said display system comprising: means for separating said first gray level signal of N bits into higher M bits and lower N-M bits; 2 tables each of which stores P x Q modification values satisfying P x Q >/= 2 ; means for selecting one of said tables by using said NM bits; means for adding said M bits and each of modification values of said selected table to generate P x Q second gray level signals; and means for supplying said second gray level signals to a display device of 2 gray levels.
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公开(公告)号：SG9395G
公开(公告)日：1995-06-16
申请号：SG9395
申请日：1995-01-21
Applicant: IBM
Inventor： SEKIYA KAZUO , SHIRAISHI YUICHI
Abstract: A method for use in a digital data display system for converting selected M gray levels in a K-gray scale to an N-gray scale (where K>N>/=M) comprising: a stage of creating a first table in which each of said M gray levels is mapped, in accordance with the order and magnitude of the relative brightness in the K-gray scale, in different M gray levels in the N-gray scale, and a stage of creating a second table in which the M gray levels in the N-gray scale mapped in said first table is mapped correspondingly to the M gray levels in said K-gray scale.
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公开(公告)号：GB2223148A
公开(公告)日：1990-03-28
申请号：GB8913014
申请日：1989-06-06
Applicant: IBM
Inventor： SEKIYA KAZUO , SHIRAISHI YUICHI
Abstract: A method for use in a digital data display system for converting selected M gray levels in a K-gray scale to an N-gray scale (where K>N>/=M) comprising: a stage of creating a first table in which each of said M gray levels is mapped, in accordance with the order and magnitude of the relative brightness in the K-gray scale, in different M gray levels in the N-gray scale, and a stage of creating a second table in which the M gray levels in the N-gray scale mapped in said first table is mapped correspondingly to the M gray levels in said K-gray scale.
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公开(公告)号：JPH04148257A
公开(公告)日：1992-05-21
申请号：JP27250790
申请日：1990-10-12
Applicant: IBM
Inventor： ARIGA NOBUO , SANO AKIRA , SHIRAISHI YUICHI
Abstract: PURPOSE: To disable access from another information processor to a storage device even when the other information processor is connected to a standard interface part by providing a means for inhibiting access through the standard interface part to the storage device. CONSTITUTION: A 1st personal computer 21 is provided with a protect signal generating circuit 51 as a means for inhibiting access to a storage device 25. The protect signal generating circuit 51 has a password memory 52, key input latch 53 and comparator circuit 54 and a password key-inputted by a key input means 31 is held by the key input latch 53 and compared with a prescribed password, which is previously stored in the password memory 52, by the comparator circuit 54. When contents held in the key input latch 53 do not match stored contents in the password memory 52, the comparator circuit 54 generates a protect signal on its output line 55. Thus, even when the other information processor is connected to a standard interface part 26, the storage device 25 can not be accessed from the other information processor.
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