公开(公告)号：JPH10207691A

公开(公告)日：1998-08-07

申请号：JP148598

申请日：1998-01-07

Applicant: IBM

Inventor： NAOAKI AOKI ,  OSAMU TAKAHASHI ,  JOEL ABRAHAM SILVERMAN ,  SAN FU DON

IPC: G06F7/38 ,  G06F7/50 ,  G06F7/505 ,  G06F7/508

Abstract: PROBLEM TO BE SOLVED: To actualize high performance with a small area by implementing logical NOR a bit line pair and a sense amplifier and generating a NOR output, connecting exclusive OR gates to corresponding NOR outputs and one specific true input signal, and generating an increased output signal. SOLUTION: Referring to an output signal B63, an input signal A63 represents the least significant digit bit, so a column B63 should execute an inverted function. The column B63 does not have 1 cell 66, so the output of a sense amplifier 72 is always 1. This a output is then exclusively ORed with an input signal A63. When the input signal A63 is 1 in binary notation, the value of the output signal B63 is 0 in binary notation and when 0, the outputs signal is 1. Referring to an output signal B62, a column B62 includes one cell, which is connected to a word line 64 corresponding to the complementary of A63, the output of an amplifier 72 is the complementary of the complementary or 63, and this is 63 true. This output is exclusively ORed with the input signal A62 and B62 is generated.