公开(公告)号：JP2005045221A

公开(公告)日：2005-02-17

申请号：JP2004180883

申请日：2004-06-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BUCKI ROBERT JOHN ,  DHONG SANG HOO ,  JOEL ABRAHAM SILVERMAN ,  OSAMU TAKAHASHI

IPC: H01L21/82 ,  G06F17/50 ,  H03K19/00 ,  H03K19/177

CPC classification number: G06F17/5054

Abstract: PROBLEM TO BE SOLVED: To shorten a signal delay and lower a power consumption by customizing a wire-segment length in a programmable logic array so that a parasitic capacitance related to an interconnection line is minimized.
SOLUTION: A first array composed of a junction leaf cell is constituted so that tiles are arranged by using at least one 1-cell and at least one 0-cell, and at least one logical expression is defined by the relative positional relationship of mutual cells configuring the array. The interconnection lines in which lengths are optimized are added to the array. Each interconnection line in which the lengths are optimized is ended by the leaf cell in the array, with which the interconnection lines are brought into contact lastly. The leaf cell can be used as a floating leaf cell. In the floating leaf cell, a pair of any junction leaf cells are electrically insulated mutually until the interconnection lines in which the lengths are optimized are added to the constitution.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：通过定制可编程逻辑阵列中的线段长度来缩短信号延迟并降低功耗，使得与互连线相关的寄生电容最小化。 解决方案：由结叶单元组成的第一阵列被构造成使得通过使用至少一个1单元和至少一个0单元布置瓦片，并且至少一个逻辑表达式由相对位置关系 的相互单元配置阵列。 将长度优化的互连线添加到阵列中。 长度优化的每个互连线由阵列中的叶单元结束，最后互连线与之接触。 叶细胞可以用作浮叶细胞。 在浮动叶细胞中，一对任何连接叶细胞相互电绝缘，直到将长度优化的互连线添加到构造中。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2009118466A

公开(公告)日：2009-05-28

申请号：JP2008252263

申请日：2008-09-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： JOSHI RAJIV VASANT ,  DHONG SANG HOO ,  JUERGEN PILLE ,  OSAMU TAKAHASHI ,  SCOTT RAYMOND COTTIER

IPC: H03K19/0185 ,  H01L21/82 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/11

CPC classification number: G11C8/08 ,  G11C11/418

Abstract: PROBLEM TO BE SOLVED: To provide a level shifter for boosting a wordline voltage and memory cell performance without making a circuit defective in operation or without causing excessive leakage. SOLUTION: A circuit and a method include a first circuit powered by a first supply voltage and second a circuit powered by a second supply voltage. A level shifter is coupled between the first circuit and the second circuit. The level shifter is configured so that a supply voltage output for a circuit including one of the first supply voltage and the second supply voltage is selected according to an input signal which depends on at least one of an operation to be performed and a component performing the operation. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于提高字线电压和存储单元性能的电平移位器，而不会使电路在操作中有缺陷或不引起过度泄漏。 解决方案：电路和方法包括由第一电源电压供电的第一电路，以及由第二电源电压供电的第二电路。 电平移位器耦合在第一电路和第二电路之间。 电平移位器被配置为使得根据输入信号选择包括第一电源电压和第二电源电压中的一个的电路的电源电压输出，该输入信号取决于要执行的操作和执行操作的组件中的至少一个 操作。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2001243071A

公开(公告)日：2001-09-07

申请号：JP2001025765

申请日：2001-02-01

Applicant: IBM

Inventor： BRIAN KING FURACCHISU ,  HOFSTEE HARM PETER ,  OSAMU TAKAHASHI

IPC: G06F9/38

Abstract: PROBLEM TO BE SOLVED: To provide a method for speculatively judging dependency and a pipe line processor. SOLUTION: A processor successively processes plural instructions. Whether or not dependency exists is judged by a speculative detecting circuit whose operation requires plural clock cycles. The speculative detecting circuit inserts one cycle pipe line stall only when responding to judgment that the speculative dependency exists.

公开(公告)号：JP2002009612A

公开(公告)日：2002-01-11

申请号：JP2001136609

申请日：2001-05-07

Applicant: IBM

Inventor： DHONG SANG HOO ,  NGO HUNG CAI ,  PARK JAEHONG ,  OSAMU TAKAHASHI

IPC: H01L21/82 ,  H03K19/173

Abstract: PROBLEM TO BE SOLVED: To provide a method and a device for mounting dynamic logic having a dynamic programmable logic gate. SOLUTION: The method and the device activate so as to complement a programmable logic array(PLA) used for a high-speed microprocessor design. A matrix, consisting of selectable cells permits powerful logic functions such as AND-OR gate functions with a minimum possible number of entries and of transistors(TRs). Employing the programmable logic array and a dynamic programmable gate can considerably improve the efficiency of logic blocks almost, without the need for adding of the circuit region.

公开(公告)号：JPH10207691A

公开(公告)日：1998-08-07

申请号：JP148598

申请日：1998-01-07

Applicant: IBM

Inventor： NAOAKI AOKI ,  OSAMU TAKAHASHI ,  JOEL ABRAHAM SILVERMAN ,  SAN FU DON

IPC: G06F7/38 ,  G06F7/50 ,  G06F7/505 ,  G06F7/508

Abstract: PROBLEM TO BE SOLVED: To actualize high performance with a small area by implementing logical NOR a bit line pair and a sense amplifier and generating a NOR output, connecting exclusive OR gates to corresponding NOR outputs and one specific true input signal, and generating an increased output signal. SOLUTION: Referring to an output signal B63, an input signal A63 represents the least significant digit bit, so a column B63 should execute an inverted function. The column B63 does not have 1 cell 66, so the output of a sense amplifier 72 is always 1. This a output is then exclusively ORed with an input signal A63. When the input signal A63 is 1 in binary notation, the value of the output signal B63 is 0 in binary notation and when 0, the outputs signal is 1. Referring to an output signal B62, a column B62 includes one cell, which is connected to a word line 64 corresponding to the complementary of A63, the output of an amplifier 72 is the complementary of the complementary or 63, and this is 63 true. This output is exclusively ORed with the input signal A62 and B62 is generated.