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公开(公告)号:JP2001346205A
公开(公告)日:2001-12-14
申请号:JP2001084465
申请日:2001-03-23
Applicant: IBM
Inventor: ERIC M FOSTER , FRANKLIN DENNIS E , LAM WAI MAN , LOSINGER RAYMOND E , NGAI CHUCK H
IPC: G06F11/10 , G11B20/10 , G11B20/18 , H03M13/37 , H04L1/00 , H04N19/00 , H04N19/89 , H04N21/43 , H04N21/44 , H04N21/4425 , H04N7/24
Abstract: PROBLEM TO BE SOLVED: To provide enhanced error recovery in the process of storing digitally transmitted audio and video signals. SOLUTION: Data damaged or lost when being sent via an irreversible compression digital transmission link are replaced with data given in relation to storage to and read from a mass storage device and/or deleted. A different procedure is used to conceal an artifact corresponding to error data based on a size of valid data and an error preceding and succeeding to an error in a data stream.
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公开(公告)号:JPS61208570A
公开(公告)日:1986-09-16
申请号:JP28321685
申请日:1985-12-18
Applicant: IBM
Inventor: NGAI CHUCK H , WATKINS GERALD J
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公开(公告)号:DE3485786T2
公开(公告)日:1993-02-04
申请号:DE3485786
申请日:1984-08-29
Applicant: IBM
Inventor: NGAI CHUCK H , WASSEL EDWARD R , WATKINS GERALD J
IPC: G06F17/16 , G06F9/302 , G06F15/78 , G06F15/347
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公开(公告)号:DE3485771T2
公开(公告)日:1993-02-04
申请号:DE3485771
申请日:1984-08-01
Applicant: IBM
Inventor: NGAI CHUCK H , WASSEL EDWARD R , WATKINS GERALD J
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公开(公告)号:DE3485771D1
公开(公告)日:1992-07-23
申请号:DE3485771
申请日:1984-08-01
Applicant: IBM
Inventor: NGAI CHUCK H , WASSEL EDWARD R , WATKINS GERALD J
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公开(公告)号:DE3485786D1
公开(公告)日:1992-07-30
申请号:DE3485786
申请日:1984-08-29
Applicant: IBM
Inventor: NGAI CHUCK H , WASSEL EDWARD R , WATKINS GERALD J
IPC: G06F17/16 , G06F9/302 , G06F15/78 , G06F15/347
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公开(公告)号:CA1233260A
公开(公告)日:1988-02-23
申请号:CA491266
申请日:1985-09-20
Applicant: IBM
Inventor: NGAI CHUCK H , WATKINS GERALD J
IPC: G06F17/16 , G06F15/80 , G06F15/347 , G06F9/28
Abstract: A parallel vector processor is disclosed. The vector processor comprises a plurality of vector registers, each vector register being subdivided in a plurality of smaller registers. A vector is stored in each vector register, the vector comprising a plurality of elements. The elements of the vector are assigned for storage in the smaller registers of the vector register. In the parallel vector processor of the present invention, assume that each vector register is subdivided into M smaller registers. The first successive M elements of an N element vector are assigned for storage in the M smaller registers of the vector register. An element processor is connected to each smaller register. Therefore, the first successive M elements of the N element vector are processed by the element processors 1 through M. The second successive M elements of the N element vector are assigned for storage in the same M smaller registers. The third successive M elements of the N element vector are assigned for storage in the M smaller registers. The second and third successive M elements of the N element vector are each processed by the element processors 1 through M. As a result, if the elements of a vector must be processed sequentially, when a second element, stored in a smaller register, is ready for processing bar an element processor, the processing of the second element need not await the completion of the processing of a first element stored in the same vector register.
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公开(公告)号:CA1208790A
公开(公告)日:1986-07-29
申请号:CA462898
申请日:1984-09-11
Applicant: IBM
Inventor: NGAI CHUCK H , WASSEL EDWARD R , WATKINS GERALD J
Abstract: A parallel vector processor is disclosed. In order to increase the performance of the parallel vector processor, the present invention decreases the time required to process the elements of a single vector stored in a vector register. Each vector register of a plurality of vector registers is subdivided into a plurality of smaller registers. A vector, stored in a vector register, comprises N elements; however, each of the smaller registers store M elements of the vector, where M is less than N. An element processor is associated with each smaller register for processing the M elements of the vectors stored in the smaller register and storing a result of the processing in a result register. Each of the smaller registers of the vector registers, and its corresponding element processor, comprise a unit. A plurality of units are connected in a parallel configuration. The element processors, associated with each unit, have been loaded with the result, the result being stored in a result register. Each of the results are processed in parallel fashion, as a result of the parallel configuration of the plurality of units. Therefore, the time required to process the elements of a single vector, stored in a vector register, is decreased.
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