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    Method, apparatus and computer program for routing data request in system-on-chip
    1.
    发明专利
    Method, apparatus and computer program for routing data request in system-on-chip 审中-公开
    方法，装置和计算机程序，用于在片上系统中路由数据请求

    公开(公告)号：JP2010015560A

    公开(公告)日：2010-01-21

    申请号：JP2009148910

    申请日：2009-06-23

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： GILDA GLENN D ,  BUTTER ADRIAN S ,  ERIC M FOSTER

    IPC: G06F12/06

    CPC classification number: G06F13/4031 ,  G06F12/1483

    Abstract: PROBLEM TO BE SOLVED: To improve system performance by making the routing of a data request within a system-on-chip (SOC) into a stream and minimizing hardware requisition.
    SOLUTION: Cross-bar segment routing and access table address remapping functions are combined within a cross-bar of a system-on-chip. In this manner, address remapping may occur prior to segment routing. One or more access table caching registers may be included for each master port. The caching registers may allow for a rapid lookup of one or more access table entries associated with each master, and allow for the simultaneous lookup by multiple masters without adding ports to the access table. A segment identifier may be stored in the caching registers to indicate how to route a matching request to the appropriate slave segment.
    COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题：通过将片内系统（SOC）中的数据请求路由到流中并最小化硬件请求来提高系统性能。

    解决方案：跨条块路由和访问表地址重映射功能在片上系统的交叉条中组合。 以这种方式，在段路由之前可能发生地址重映射。 每个主端口可能包含一个或多个访问表缓存寄存器。 高速缓存寄存器可以允许快速查找与每个主机相关联的一个或多个访问表条目，并允许多个主机同时查找而不向接入表添加端口。 段标识符可以存储在高速缓存寄存器中，以指示如何将匹配请求路由到适当的从段。 版权所有（C）2010，JPO＆INPIT

    SYSTEM AND METHOD FOR MERGING PLURAL AUDIO STREAMS
    3.
    发明专利
    SYSTEM AND METHOD FOR MERGING PLURAL AUDIO STREAMS 失效

    公开(公告)号：JP2000308015A

    公开(公告)日：2000-11-02

    申请号：JP2000072198

    申请日：2000-03-15

    Applicant: IBM

    Inventor： RICHARD EUGENE ANDERSON ,  ERIC M FOSTER ,  DENNIS EDWARD FRANKLIN

    IPC: H04N5/92 ,  G10L19/00 ,  H04H60/04 ,  H04N5/93

    Abstract: PROBLEM TO BE SOLVED: To provide a synthesized device where plural independent digital audio streams are decoded and merged by mixing a first decoded stream and a second formatted stream and outputting it as a merged audio signal. SOLUTION: An audio PCM reproduction macro 25 for formatting a second audio PCM data taken out from a system memory 22 is supplied for mixing it with a first audio PCM signal output from an audio decoder 26 which is not compressed. Outputs from the audio decoder 26 and the audio PCM reproduction macro 25 are sent to a mixer 28 for merging the two audio streams to a single audio output signal 13. Output from a video decoder 18 contains a decoded video signal 12. The video signal 12 and the audio output signal 13 are sent for displaying them to a viewer.

    METHOD FOR UPDATING PLURAL REGISTERS, PLURAL-REGISTER SYSTEM AND PLURAL-CLOCK SYSTEM
    4.
    发明专利
    METHOD FOR UPDATING PLURAL REGISTERS, PLURAL-REGISTER SYSTEM AND PLURAL-CLOCK SYSTEM 失效

    公开(公告)号：JP2000004443A

    公开(公告)日：2000-01-07

    申请号：JP7558099

    申请日：1999-03-19

    Applicant: IBM

    Inventor： ERIC M FOSTER ,  LEE WILLIAM R ,  RONALD S SVECK

    IPC: H04N7/32 ,  G06F12/02 ,  H04J3/00 ,  H04J3/06

    Abstract: PROBLEM TO BE SOLVED: To provide separate system time clock (STC) registers, which can be independently updated, by executing any one of the independent update and synchronous update of first and second count values in first and second counter registers corresponding to first and second address values. SOLUTION: When the address values of ADDR-VID register 501 and an ADDR-AUD register 511 are different, a host controller separately writes updating in an STC-VID register and an STC-AUD register. By making equal the address values of the ADDR-VID register 501 and ADDR-AUD register 511, one STC value is simultaneously written in both the STC-VID register 500 and the STC-AUD register 510. Further, by writing the different address value in any one of the ADDR-VID register 501 and ADDR-AUD register 511 after synchronizing both the registers 500 and 510, the independence of counters is recovered.

    DIGITAL SYSTEM AND METHOD
    7.
    发明专利
    DIGITAL SYSTEM AND METHOD 失效

    公开(公告)号：JP2001290762A

    公开(公告)日：2001-10-19

    申请号：JP2001073048

    申请日：2001-03-14

    Applicant: IBM

    Inventor： ERIC M FOSTER ,  STEVEN B HERNDON ,  ERIC E LETTER ,  RONALD S SVECK

    IPC: G06F13/362 ,  G06F13/00 ,  G09G1/16 ,  G09G5/00

    Abstract: PROBLEM TO BE SOLVED: To provide a method and a structure for dynamically blocking access of a request signal to a shared bus. SOLUTION: The shared bus manages a request for access to an address space. A nonreal time master and a real time master compete about their requests for address space access by presenting the address access requests to the shared bus. An access dynamic block by R with respect to the shared bus is accomplished by using a request limiter. The request limiter is a device connected to a real time clock and uses algorithm for deciding a time when the access of R to the shared bus is made performable or nullified. The algorithm uses a window scheme that allows the access of R to the shared bus every N-th clock cycle. Here, the value of an integer N can be supplied to the request limiter by the real time master.

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