公开(公告)号：GB2603339A

公开(公告)日：2022-08-03

申请号：GB202203969

申请日：2020-08-07

Applicant: IBM

Inventor： MICHAEL KLEIN ,  NICOL HOFMANN ,  CEDRIC LICHTENAU ,  OSHER YIFRACH

IPC: G06F15/80

Abstract: A system for processing instructions with extended results includes a first instruction execution unit having a first result bus for execution of processor instructions. The system further includes a second instruction execution unit having a second result bus for execution of processor instructions. The first instruction execution unit is configured to selectively send a portion of results calculated by the first instruction execution unit to the second instruction execution unit during prosecution of a processor instruction if the second instruction execution unit is not used for executing the processor instruction and if the received processor instruction produces a result having a data width greater than the width of the first result bus. The second instruction execution unit is configured to receive the portion of results calculated by the first instruction execution unit and put the received results on the second results bus.

公开(公告)号：GB2573685A

公开(公告)日：2019-11-13

申请号：GB201910346

申请日：2018-01-08

Applicant: IBM

Inventor： CEDRIC LICHTENAU ,  MICHAEL KLEIN ,  NICOL HOFMANN

IPC: G06F7/48

Abstract: A circuit includes reconfigurable units that are reconfigurable to compute a combined result. A first intermediate result of a first reconfigurable unit of the reconfigurable units is exchanged with a second intermediate result of the second reconfigurable unit of the reconfigurable units. The first reconfigurable unit computes a first portion of the combined result utilizing the second intermediate result. The second reconfigurable unit of the reconfigurable units computes a second portion of the combined result utilizing the first intermediate result.

公开(公告)号：GB2573685B

公开(公告)日：2020-04-22

申请号：GB201910346

申请日：2018-01-08

Applicant: IBM

Inventor： CEDRIC LICHTENAU ,  MICHAEL KLEIN ,  NICOL HOFMANN

IPC: G06F7/48

Abstract: A circuit includes reconfigurable units that are reconfigurable to compute a combined result. A first intermediate result of a first reconfigurable unit of the reconfigurable units is exchanged with a second intermediate result of the second reconfigurable unit of the reconfigurable units. The first reconfigurable unit computes a first portion of the combined result utilizing the second intermediate result. The second reconfigurable unit of the reconfigurable units computes a second portion of the combined result utilizing the first intermediate result.