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公开(公告)号：GB2630547A
公开(公告)日：2024-11-27
申请号：GB202412923
申请日：2023-03-21
Applicant: IBM
Inventor： MICHAEL KLEIN , PETRA LEBER , CEDRIC LICHTENAU , STEFAN PAYER , KERSTIN SCHELM
Abstract: Rounding hexadecimal floating point numbers using binary incrementors, including: incrementing, by a first incrementor, a first subset of bits of an operand comprising a binary hexadecimal floating point operand; incrementing, by a second incrementor, a second subset of bits of the operand; generate an intermediate result based on a carryout of the second incrementor; and generate an incremented result based on a carryout of the first incrementor and one or more of: a first bit of the intermediate result or the carryout of the second incrementor.
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公开(公告)号：GB2630547B
公开(公告)日：2025-04-09
申请号：GB202412923
申请日：2023-03-21
Applicant: IBM
Inventor： MICHAEL KLEIN , PETRA LEBER , CEDRIC LICHTENAU , STEFAN PAYER , KERSTIN SCHELM
Abstract: Rounding hexadecimal floating point numbers using binary incrementors, including: incrementing, by a first incrementor, a first subset of bits of an operand comprising a binary hexadecimal floating point operand; incrementing, by a second incrementor, a second subset of bits of the operand; generate an intermediate result based on a carryout of the second incrementor; and generate an incremented result based on a carryout of the first incrementor and one or more of: a first bit of the intermediate result or the carryout of the second incrementor.
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公开(公告)号：GB2572719B
公开(公告)日：2020-05-20
申请号：GB201909646
申请日：2017-11-30
Applicant: IBM
Inventor： SILVIA MELITTA MUELLER , PETRA LEBER , CEDRIC LICHTENAU
Abstract: A circuit is provided which includes arithmetic computation logic configured to add or subtract operands of variable length to produce a result in a sign-magnitude data format. The circuit also includes an overflow detector to provide an overflow signal indicative of whether the result fits within a specified result length l. The overflow detector operates on the operands prior to the arithmetic computation logic producing the result to determine, independent of the result produced by the arithmetic computation logic, whether the result fits within the specified result length l.
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公开(公告)号：GB2528443B
公开(公告)日：2016-12-14
申请号：GB201412875
申请日：2014-07-21
Applicant: IBM
Inventor： CEDRIC LICHTENAU , SILVIA MELITTA MUELLER , STEVEN R CARLOUGH
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公开(公告)号：IL302916A
公开(公告)日：2023-07-01
申请号：IL30291623
申请日：2023-05-14
Applicant: IBM , ERIC MARK SCHWARZ , PETRA LEBER , KERSTIN CLAUDIA SCHELM , SILVIA MELITTA MUELLE , REID COPELAND , XIN GUO , CEDRIC LICHTENAU
Inventor： ERIC MARK SCHWARZ , PETRA LEBER , KERSTIN CLAUDIA SCHELM , SILVIA MELITTA MUELLE , REID COPELAND , XIN GUO , CEDRIC LICHTENAU
Abstract: An instruction to perform scaling, converting and splitting operations is executed. The executing the instruction includes scaling an input value in one format to provide a scaled result. The scaled result is converted from the one format to provide a converted result in another format. The converted result is split into multiple parts, and one or more parts of the multiple parts are placed in a selected location.
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Patent Agency Ranking
公开(公告)号：GB2595191B
公开(公告)日：2022-09-21
申请号：GB202112124
申请日：2020-01-27
Applicant: IBM
Inventor： CEDRIC LICHTENAU , REID COPELAND , PETRA LEBER , JONATHAN BRADBURY , SILVIA MELITTA MUELLER , XIN GUO
Abstract: Digit validation check control for execution of an instruction. A process obtains an instruction to perform operation(s) using input value(s). The instruction includes a no validation indicator for controlling whether digit validation check control is enabled for execution of the instruction. The process executes the instruction, including determining, based on the no validation indicator, whether digit validation check control is enabled for execution of the instruction, and performing processing based on the determining. Based on the no validation indicator being set to a defined value, digit validation check control is enabled and the processing includes forcing a digit check error indicator output by the executing to indicate no digit check error with respect to the at least one input value.
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公开(公告)号：GB2602405A
公开(公告)日：2022-06-29
申请号：GB202203285
申请日：2020-08-07
Applicant: IBM
Inventor： RAZVAN FIGULI , STEFAN PAYER , CEDRIC LICHTENAU , KERSTIN SCHELM
IPC: G06F11/07
Abstract: A method for detecting faults in substring search operations includes providing, using a processor unit including vector registers of M vector elements each, anMxM Matrix of comparators for characterwise comparison of the elements of a reference string stored in a first one of the vector registers and a target string stored in a second one of the vector registers. A vector element is an n-bit element for encoding a character.A resulting bit vector is generated using comparison performed by the MxM matrix. The resulting bit vector indicates characters of the target string that fully match the reference string and indicates characters of the target string that partially match the reference string. Fault detection in the substring search operations is performed by utilizing the resulting bit vector.
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公开(公告)号：GB2573685B
公开(公告)日：2020-04-22
申请号：GB201910346
申请日：2018-01-08
Applicant: IBM
Inventor： CEDRIC LICHTENAU , MICHAEL KLEIN , NICOL HOFMANN
IPC: G06F7/48
Abstract: A circuit includes reconfigurable units that are reconfigurable to compute a combined result. A first intermediate result of a first reconfigurable unit of the reconfigurable units is exchanged with a second intermediate result of the second reconfigurable unit of the reconfigurable units. The first reconfigurable unit computes a first portion of the combined result utilizing the second intermediate result. The second reconfigurable unit of the reconfigurable units computes a second portion of the combined result utilizing the first intermediate result.
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公开(公告)号：GB2630701A
公开(公告)日：2024-12-04
申请号：GB202411765
申请日：2023-02-20
Applicant: IBM
Inventor： CEDRIC LICHTENAU , VIJAYALAKSHMI SRINIVASAN , SUNIL K SHUKLA , SWAGATH VENKATARAMANI , KAILASH GOPALAKRISHNAN , HOLGER HORBACH , RAZVAN PETER FIGULI , WEI WANG , YULONG LI , MARTIN LUTZ
Abstract: Processing input data for transmittal to a data consumer such as an artificial intelligence engine is performed by arranging the input data into a uniform structure made up of sticks of data combined to form pages of sticks. A stick is any well-sized set of input data elements whereby the size of the stick is fixed. A masking pattern is established for sticks of data having certain ranges of invalid data for consumption of partial sticks while maintaining validity of the input data being transferred. The mask pattern is derived based on set-active-mask-and-value (SAMV) instructions. The derived mask pattern is carried forward for subsequent load instructions to the data consumer.
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公开(公告)号：GB2603339A
公开(公告)日：2022-08-03
申请号：GB202203969
申请日：2020-08-07
Applicant: IBM
Inventor： MICHAEL KLEIN , NICOL HOFMANN , CEDRIC LICHTENAU , OSHER YIFRACH
IPC: G06F15/80
Abstract: A system for processing instructions with extended results includes a first instruction execution unit having a first result bus for execution of processor instructions. The system further includes a second instruction execution unit having a second result bus for execution of processor instructions. The first instruction execution unit is configured to selectively send a portion of results calculated by the first instruction execution unit to the second instruction execution unit during prosecution of a processor instruction if the second instruction execution unit is not used for executing the processor instruction and if the received processor instruction produces a result having a data width greater than the width of the first result bus. The second instruction execution unit is configured to receive the portion of results calculated by the first instruction execution unit and put the received results on the second results bus.
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