公开(公告)号：GB2630547A

公开(公告)日：2024-11-27

申请号：GB202412923

申请日：2023-03-21

Applicant: IBM

Inventor： MICHAEL KLEIN ,  PETRA LEBER ,  CEDRIC LICHTENAU ,  STEFAN PAYER ,  KERSTIN SCHELM

IPC: G06F7/483 ,  G06F7/499 ,  G06F7/74

Abstract: Rounding hexadecimal floating point numbers using binary incrementors, including: incrementing, by a first incrementor, a first subset of bits of an operand comprising a binary hexadecimal floating point operand; incrementing, by a second incrementor, a second subset of bits of the operand; generate an intermediate result based on a carryout of the second incrementor; and generate an incremented result based on a carryout of the first incrementor and one or more of: a first bit of the intermediate result or the carryout of the second incrementor.

公开(公告)号：GB2603339A

公开(公告)日：2022-08-03

申请号：GB202203969

申请日：2020-08-07

Applicant: IBM

Inventor： MICHAEL KLEIN ,  NICOL HOFMANN ,  CEDRIC LICHTENAU ,  OSHER YIFRACH

IPC: G06F15/80

Abstract: A system for processing instructions with extended results includes a first instruction execution unit having a first result bus for execution of processor instructions. The system further includes a second instruction execution unit having a second result bus for execution of processor instructions. The first instruction execution unit is configured to selectively send a portion of results calculated by the first instruction execution unit to the second instruction execution unit during prosecution of a processor instruction if the second instruction execution unit is not used for executing the processor instruction and if the received processor instruction produces a result having a data width greater than the width of the first result bus. The second instruction execution unit is configured to receive the portion of results calculated by the first instruction execution unit and put the received results on the second results bus.

公开(公告)号：GB2573685A

公开(公告)日：2019-11-13

申请号：GB201910346

申请日：2018-01-08

Applicant: IBM

Inventor： CEDRIC LICHTENAU ,  MICHAEL KLEIN ,  NICOL HOFMANN

IPC: G06F7/48

Abstract: A circuit includes reconfigurable units that are reconfigurable to compute a combined result. A first intermediate result of a first reconfigurable unit of the reconfigurable units is exchanged with a second intermediate result of the second reconfigurable unit of the reconfigurable units. The first reconfigurable unit computes a first portion of the combined result utilizing the second intermediate result. The second reconfigurable unit of the reconfigurable units computes a second portion of the combined result utilizing the first intermediate result.

公开(公告)号：GB2573685B

公开(公告)日：2020-04-22

申请号：GB201910346

申请日：2018-01-08

Applicant: IBM

Inventor： CEDRIC LICHTENAU ,  MICHAEL KLEIN ,  NICOL HOFMANN

IPC: G06F7/48

Abstract: A circuit includes reconfigurable units that are reconfigurable to compute a combined result. A first intermediate result of a first reconfigurable unit of the reconfigurable units is exchanged with a second intermediate result of the second reconfigurable unit of the reconfigurable units. The first reconfigurable unit computes a first portion of the combined result utilizing the second intermediate result. The second reconfigurable unit of the reconfigurable units computes a second portion of the combined result utilizing the first intermediate result.

公开(公告)号：GB2630547B

公开(公告)日：2025-04-09

申请号：GB202412923

申请日：2023-03-21

Applicant: IBM

Inventor： MICHAEL KLEIN ,  PETRA LEBER ,  CEDRIC LICHTENAU ,  STEFAN PAYER ,  KERSTIN SCHELM

IPC: G06F7/483 ,  G06F7/499 ,  G06F7/74

Abstract: Rounding hexadecimal floating point numbers using binary incrementors, including: incrementing, by a first incrementor, a first subset of bits of an operand comprising a binary hexadecimal floating point operand; incrementing, by a second incrementor, a second subset of bits of the operand; generate an intermediate result based on a carryout of the second incrementor; and generate an incremented result based on a carryout of the first incrementor and one or more of: a first bit of the intermediate result or the carryout of the second incrementor.

公开(公告)号：GB2530990A

公开(公告)日：2016-04-13

申请号：GB201417582

申请日：2014-10-06

Applicant: IBM

Inventor： MICHAEL KROENER ,  SILVIA MELITTA MUELLER ,  STEVEN R CARLOUGH ,  MICHAEL KLEIN ,  KERSTIN SCHELM ,  PETRA LEBER ,  JUERGEN HAESS

IPC: G06F7/485 ,  G06F7/491

Abstract: A decimal floating point unit for performing add or subtract calculations on a first (100) and second operand (101) comprising unpacking S200 the first and second operand such as by formatting 128 bit width mantissa to be 136 bit wide; conditionally swapping S202 the first and second operand, if an exponent (104) of the first operand is less than an exponent (105) of the second operand, and aligning S204, S206 the operands based on the exponent difference and a number of leading zeroes in the operand with the larger exponent. Adding or subtracting the operands S208 is performed on the aligned operands with normalizing and rounding of the result which is then packed S210. Binary floating point arithmetic can also be performed on the decimal floating point unit which may be pipelined.