公开(公告)号：US3369132A

公开(公告)日：1968-02-13

申请号：US23750162

申请日：1962-11-14

Applicant: IBM

Inventor： FANG FRANK F ,  TSU-HSING YEH ,  NIEN YU HWA

IPC: H01L21/00 ,  H01L21/18 ,  H01L27/10 ,  H01L29/00 ,  H01L29/74 ,  H01L31/12 ,  H01L31/173

CPC classification number: H01L31/12 ,  H01L21/00 ,  H01L21/185 ,  H01L27/10 ,  H01L29/00 ,  H01L29/74 ,  H01L31/173 ,  Y10S148/072

公开(公告)号：DE1564151A1

公开(公告)日：1969-07-24

申请号：DEJ0030835

申请日：1966-05-14

Applicant: IBM

Inventor： FU FANG FRANK ,  NIEN YU HWA ,  JOHN WALKER EDWARD

IPC: H01L27/088 ,  H01L21/00 ,  H01L21/22 ,  H01L21/316 ,  H01L21/8234 ,  H01L21/8236 ,  H01L29/00 ,  H01L29/78 ,  H01L11/14

Abstract: A method for manufacturing a field-effect, isolated-barrier transistor, comprising the steps of: forming by diffusion separate parts, of a first type of conductivity, on the surface of an elementary semiconductor wafer of the opposite conductivity type; forming an insulating layer at least in the intermediate part of said surface lying between said diffused portions separated and defining a conduit channel therebetween, having a given surface potential the interfacial zone between said insulating layer and said intermediate portion of said surface. said wafer; and forming on said insulating layer a barrier electrode for applying electric fields to said intermediate surface portion; method characterized by the improvement comprising the step of passing through diffusion an impurity material of the acceptor type, through said insulating layer and until penetrating a narrow layer of said intermediate surface part before forming said barrier electrode, for control the surface potential in said interfacial zone. (Machine-translation by Google Translate, not legally binding)

公开(公告)号：DE1489031B1

公开(公告)日：1972-01-05

申请号：DE1489031

申请日：1964-11-05

Applicant: IBM

Inventor： NIEN YU HWA

IPC: H01L21/00 ,  H01L29/00 ,  H01L29/732 ,  H01L11/06

Abstract: 1,026,019. Transistors. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 19, 1964 [Nov. 8, 1963], No. 42536/64. Heading H1K. The effective collector-base junction is restricted to an area 12 by the interpolation of a layer 11 of intrinsic-conductivity material.

公开(公告)号：DE1464713A1

公开(公告)日：1970-04-16

申请号：DE1464713

申请日：1963-11-08

Applicant: IBM

Inventor： FU FAN FRANK ,  NIEN YU HWA ,  YEH TSU-HSING

IPC: H01L21/00 ,  H01L21/18 ,  H01L27/10 ,  H01L29/00 ,  H01L29/74 ,  H01L31/12 ,  H01L31/173

公开(公告)号：DE1589919A1

公开(公告)日：1970-06-04

申请号：DE1589919

申请日：1967-01-16

Applicant: IBM

Inventor： NIEN YU HWA

IPC: H01L21/8234 ,  H01L23/535 ,  H01L27/00 ,  H01L27/112 ,  H03K17/693 ,  G06F7/38

Abstract: 1,150,336. Decimal half-adders. INTERNATIONAL BUSINESS MACHINES CORP. 17 Jan., 1967 [17 Jan., 1966], No. 2358/67. Heading G4A. [Also in Division H1] A switching matrix is formed by an array of field-effect transistors arranged in rows and columns on a common semi-conductor substrate. The transistors in each row have a common source electrode and those in each column have a common gate electrode. Means are provided for selectively applying drive pulses to the common source electrodes as are means for selectively applying gating pulses to the common gate electrodes. The embodiments describe the use of IGFETs operating in the enhancement mode, but it is stated that unipolar transistors may be used. In the construction of Fig. 1 the source diffusions S0-S9, S 1 0-S 1 9 and drain diffusions D are made simultaneously by diffusion of phosphorus into a high resistivity silicon wafer through holes in a genetic silica coating which regrows during the process. The gate electrodes G0-G9, G 1 0-G 1 9 are formed by completely coating the insulated wafer with aluminium which is then selectively removed. The matrix consists of transistors T00-T99. The wafer additionally contains driver transistors DR0-DR9 whose drain electrodes are respectively formed by the extended source diffusions S0-S9 of the matrix. The load R associated with a particular transistor is energized along when the appropriate driver transistor DR and gate G are activated by conventional pulse sources PS2, PS1. In the similar decimal half-adder of Fig. 4 the source and drain electrodes of the matrix and its driving transistors are made by a first diffusion process. The " horizontal " crossunder connectors 0-9 and 0-18 may be formed by a surface metallization pattern over the insulating oxide or may be formed by a second diffusion process yielding N + patterns in the surface of the wafer. In the latter case the linking " vertical " cross-unders are then made by surface metallization at the same time as the formation of the gate electrodes G0-G9, G 1 0-G 1 9 of the matrix and driving transistors. In operation a decimal digit is fed in from source DS 1 simultaneously with a second digit from the other source DS2, and the cross-under 0-18 corresponding to the sum of the digits is energized.

公开(公告)号：DE1288198B

公开(公告)日：1969-01-30

申请号：DEI0029029

申请日：1965-09-21

Applicant: IBM

Inventor： NIEN YU HWA

IPC: H01L21/205 ,  H01L7/34

Abstract: 1,045,108. Transistors. INTERNATIONAL BUSINESS MACHINES CORPORATION. Aug. 24, 1965 [Sept. 23, 1964], No. 36418/65. Heading H1K. A transistor is formed by a process comprising epitaxially growing a semi-conductor body having two regions of different basic material, said materials having different band gaps, and heating the body to cause diffusion from one region to the other so as to change the other region to the opposite conductivity type. In an embodiment, a layer of Ge is grown epitaxially on a substrate of GaAs to give a PP heterojunction. The device is then heated under arsenic pressure in a closed tube to 500‹ to 700‹ C., thus causing some As to diffuse out of the GaAs and into the germanium giving a device as shown in Fig. 2B. The device formed is a wide-gap emitter, drift field base transistor. In another embodiment a GaP substrate has a Si layer grown thereon and some of the phosphorus is subsequently diffused into the silicon.