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1.发明公开STRUCTURE AND METHOD OF FABRICATING HIGH-DENSITY, TRENCH-BASED NON-VOLATILE RANDOM ACCESS SONOS MEMORY CELLS FOR SOC APPLICATIONS 审中-公开生产高POET的结构和方法，抢基于不挥发SONOS RAM单元进行SoC应用
公开(公告)号：EP1869709A4
公开(公告)日：2008-07-16
申请号：EP06749815
申请日：2006-04-12
Applicant: IBM
Inventor： MANDELMAN JACK , HO HERBERT , NING TAK , OTANI YOICHI
IPC: H01L21/8247 , G11C16/04 , H01L27/115 , H01L29/792
CPC classification number: H01L27/115 , G11C16/0466 , H01L27/0207 , H01L27/105 , H01L27/11568 , H01L27/1157 , H01L27/11573 , H01L29/792 , H01L29/7926
Abstract: The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as method of fabricating the same, hi one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located within a trench structure having trench depth from 1 to 2 µm and the memory transistor is located on a surface of a semiconductor substrate adjoining the trench structure. In another embodiment, a 2-Tr SONOS memory cell is provided in which both the select transistor and the memory transistor are located within a trench structure having the depth mentioned above.
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2.发明申请STRUCTURE AND METHOD OF FABRICATING HIGH-DENSITY, TRENCH-BASED NON-VOLATILE RANDOM ACCESS SONOS MEMORY CELLS FOR SOC APPLICATIONS 审中-公开用于SOC应用的高密度，基于TRENCH的非易失性随机接入SONOS存储器细胞的构造和方法
公开(公告)号：WO2006110781A3
公开(公告)日：2007-04-19
申请号：PCT/US2006013561
申请日：2006-04-12
Applicant: IBM , MANDELMAN JACK , HO HERBERT , NING TAK , OTANI YOICHI
Inventor： MANDELMAN JACK , HO HERBERT , NING TAK , OTANI YOICHI
IPC: H01L29/76
CPC classification number: H01L27/115 , G11C16/0466 , H01L27/0207 , H01L27/105 , H01L27/11568 , H01L27/1157 , H01L27/11573 , H01L29/792 , H01L29/7926
Abstract: The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as method of fabricating the same, hi one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located within a trench structure having trench depth from 1 to 2 µm and the memory transistor is located on a surface of a semiconductor substrate adjoining the trench structure. In another embodiment, a 2-Tr SONOS memory cell is provided in which both the select transistor and the memory transistor are located within a trench structure having the depth mentioned above.
Abstract translation: 本发明提供了具有随机访问的存储位置的双晶体管氧化硅 - 氧化物 - 氧化物半导体（2-Tr SONOS）非易失性存储单元及其制造方法。在一个实施例中，2-Tr SONOS 提供了选择晶体管位于具有1至2μm的沟槽深度的沟槽结构内的单元，并且存储晶体管位于与沟槽结构相邻的半导体衬底的表面上。 在另一个实施例中，提供了2-Tr SONOS存储单元，其中选择晶体管和存储晶体管都位于具有上述深度的沟槽结构内。
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