公开(公告)号：EP1869709A4

公开(公告)日：2008-07-16

申请号：EP06749815

申请日：2006-04-12

Applicant: IBM

Inventor： MANDELMAN JACK ,  HO HERBERT ,  NING TAK ,  OTANI YOICHI

IPC: H01L21/8247 ,  G11C16/04 ,  H01L27/115 ,  H01L29/792

CPC classification number: H01L27/115 ,  G11C16/0466 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/792 ,  H01L29/7926

Abstract: The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as method of fabricating the same, hi one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located within a trench structure having trench depth from 1 to 2 µm and the memory transistor is located on a surface of a semiconductor substrate adjoining the trench structure. In another embodiment, a 2-Tr SONOS memory cell is provided in which both the select transistor and the memory transistor are located within a trench structure having the depth mentioned above.

公开(公告)号：WO0137325A9

公开(公告)日：2002-07-04

申请号：PCT/US0031227

申请日：2000-11-13

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： CLEVENGER LAWRENCE ,  COSTRINI GREG ,  DOBUZINSKY DAVE ,  OTANI YOICHI ,  RUPP THOMAS ,  SARDESAI VIRAJ

IPC: H01L21/311 ,  H01L21/768

CPC classification number: H01L21/31116 ,  H01L21/76802

Abstract: A damascene method of forming conductive lines in an integrated circuit chip. Trenches are etched by a plasma formed by capacitively coupling a gas mixture at 500 to 3000watts under a pressure of 50 - 400mTorr. The gas mixture includes 2 - 30sccm of C4F8, 20 - 80sccm of CO, 2 - 30sccm of O2 and 50 - 400sccm of Ar. Gas flow can be adjusted to an optimum level, thereby achieving a high degree of uniformity. Wafers falling below a selected uniformity may be reworked. A damascene wiring layer formed in the trenches with an acceptable flow exhibit a high degree of sheet resistance uniformity and improved line to line shorts yield.

Abstract translation: 在集成电路芯片中形成导线的镶嵌方法。 通过在压力为50-400mTorr的500-3000瓦电容耦合气体混合物形成的等离子体蚀刻沟槽。 气体混合物包括2 - 30sccm的C4F8，20 - 80sccm的CO，2 - 30sccm的O2和50 - 400sccm的Ar。 可以将气体流量调节到最佳水平，从而实现高度的均匀性。 低于所选均匀度的晶片可能会重新加工。 在具有可接受流动的沟槽中形成的镶嵌布线层表现出高度的薄层电阻均匀性和改善的线对线短路产量。

公开(公告)号：WO2006110781A3

公开(公告)日：2007-04-19

申请号：PCT/US2006013561

申请日：2006-04-12

Applicant: IBM ,  MANDELMAN JACK ,  HO HERBERT ,  NING TAK ,  OTANI YOICHI

Inventor： MANDELMAN JACK ,  HO HERBERT ,  NING TAK ,  OTANI YOICHI

IPC: H01L29/76

CPC classification number: H01L27/115 ,  G11C16/0466 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/792 ,  H01L29/7926

Abstract: The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as method of fabricating the same, hi one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located within a trench structure having trench depth from 1 to 2 µm and the memory transistor is located on a surface of a semiconductor substrate adjoining the trench structure. In another embodiment, a 2-Tr SONOS memory cell is provided in which both the select transistor and the memory transistor are located within a trench structure having the depth mentioned above.

Abstract translation: 本发明提供了具有随机访问的存储位置的双晶体管氧化硅 - 氧化物 - 氧化物半导体（2-Tr SONOS）非易失性存储单元及其制造方法。在一个实施例中，2-Tr SONOS 提供了选择晶体管位于具有1至2μm的沟槽深度的沟槽结构内的单元，并且存储晶体管位于与沟槽结构相邻的半导体衬底的表面上。 在另一个实施例中，提供了2-Tr SONOS存储单元，其中选择晶体管和存储晶体管都位于具有上述深度的沟槽结构内。

公开(公告)号：WO0137325A2

公开(公告)日：2001-05-25

申请号：PCT/US0031227

申请日：2000-11-13

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： CLEVENGER LAWRENCE ,  COSTRINI GREG ,  DOBUZINSKY DAVE ,  OTANI YOICHI ,  RUPP THOMAS ,  SARDESAI VIRAJ

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/00

CPC classification number: H01L21/31116 ,  H01L21/76802

Abstract: A damascene method of forming conductive lines in an integrated circuit chip. Trenches are etched by a plasma formed by capacitively coupling a gas mixture at 500 to 3000watts under a pressure of 50 - 400mTorr. The gas mixture includes 2 - 30sccm of C4F8 2

Abstract translation: 在集成电路芯片中形成导线的镶嵌方法。 通过在压力为50-400mTorr的500-3000瓦电容耦合气体混合物形成的等离子体蚀刻沟槽。 气体混合物包括2-30sccm的C 4 F 8，20-80sccm的CO，2-30sccm的O> 2和50-400sccm的Ar。 可以将气体流量调节到最佳水平，从而实现高度的均匀性。 低于所选均匀度的晶片可能会重新加工。 在具有可接受流动的沟槽中形成的镶嵌布线层表现出高度的薄层电阻均匀性和改善的线对线短路产量。

公开(公告)号：JP2007150317A

公开(公告)日：2007-06-14

申请号：JP2006317746

申请日：2006-11-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DOBUZINSKY DAVID M ,  HO HERBERT L ,  MANDELMAN JACK A ,  OTANI YOICHI

IPC: H01L21/8247 ,  H01L21/265 ,  H01L21/76 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/792 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/7926

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is formed in a semiconductor-on-insulator (SOI) substrate. SOLUTION: A memory cell comprises: a semiconductor-on-insulator substrate including a top semiconductor layer and a bottom semiconductor layer that are separated from each other by a buried insulating layer; and at least one vertical trench SONOS memory cell located in the semiconductor-on-insulator substrate. The at least one vertical trench SONOS memory cell comprises: a source diffusion located beneath the vertical trench; a selection gate channel located on one side of the vertical trench; an outward-diffused/Si-containing bridge located on and in contact with the selection gate channel; and a silicided doped region located adjacent to and in contact with an upper portion of the bridge. The bridge is present in the top semiconductor layer, the buried insulating layer, and the bottom semiconductor layer. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 解决的问题：提供一种半导体存储器件，其中在绝缘体上半导体（SOI）衬底中形成垂直沟槽半导体氧化物 - 氮化物 - 氧化物半导体（SONOS）存储单元。 解决方案：存储单元包括：绝缘体上半导体衬底，包括通过掩埋绝缘层彼此分离的顶部半导体层和底部半导体层; 以及位于绝缘体上半导体衬底中的至少一个垂直沟道SONOS存储器单元。 所述至少一个垂直沟道SONOS存储单元包括：位于垂直沟槽下方的源极扩散; 位于所述垂直沟槽的一侧上的选择栅极沟道; 位于选择栅极通道上并与选择栅极通道接触的向外扩散/含Si桥; 以及位于与桥的上部相邻并与其接触的硅化物掺杂区域。 该桥存在于顶部半导体层，埋入绝缘层和底部半导体层中。 版权所有（C）2007，JPO＆INPIT