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公开(公告)号：GB2165975B
公开(公告)日：1988-07-20
申请号：GB8525903
申请日：1985-10-21
Applicant: IBM
Inventor： BRANTLEY JR WILLIAM CAIN , MCAULIFEE KEVIN PATRICK , NORTON VERN ALAN
Abstract: Method and Apparatus for dynamically partitioning a storage system into a global storage efficiently accessible by a number of processors connected to a network, and local storage efficiently accessible by individual processors, including means for interleaving storage references by a processor; means under the control of each processor for controlling the means for interleaving storage references and means for dynamically directing storage references to first or second portions of storage.In operation, a virtual address from a processor is stored in VAR 242 and comprises a segment and/or page index (S/P 1) 244, a page offset (PO) 246 and word offset (WO) 248. The S/P I is used in a conventional way as an index into the storage mapping tables 270 to provide a real address which is placed in register 250. Unique to this disclosure, the table look-up also provides a quantity, the interleave amount, which indicates whether the real address is in local or global storage and, which in the latter event, is used to derive the absolute addresses. The low order bits of the real address may be hashed using Remap 252 to introduce a random element into a sequence of consecutive addresses. The real address after mapping, excluding the word offset (WO) is passed to right rotate device 256 which is controlled by the interleave amount. The width of the field to be rotated and the amount the field is to be rotated are specified by the interleave amount. The derived absolute addresses are entered in register 258 and are passed for use onto a communication network interconnecting the processors and the storage system.
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公开(公告)号：DE68921365T2
公开(公告)日：1995-10-05
申请号：DE68921365
申请日：1989-03-22
Applicant: IBM
IPC: G06F15/167 , G06F12/12 , G06F13/16 , G06F15/173 , H04L12/56 , G06F15/16 , G06F12/02 , G06F9/46
Abstract: An interconnection network management architecture for use with a large shared memory multiprocessor computing system including a plurality of processors and a plurality of separately addressable main memory modules. Two parallel, interconnection networks are provided each capable of interconnecting any processor to any memory module, and each having different latency characteristics. A Hot-Spot detection means is associated with each main memory module for detecting when a particular address in that module has become a Hot Spot and includes a first memory for storing all detected Hot Spots. A diverter element is associated with each processor for selectively routing memory requests over either said first or second memory network con tingent on its status as a Hot Spot. A second memory is included in each diverter element for storing all Hot Spots detected by the detector elements. A control mechanism determines if any current main memory address is a listed Hot Spot within said second memory and, if so, causes the main memory reference to be transmitted to the memory system over a selected interconnection network. Another component of this mechanism determines if a particular address has been accessed a sufficient number of times within a given timeframe to be deemed a Hot Spot and removes Hot Spots from both the first and second memories when necessary.
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公开(公告)号：DE68923055D1
公开(公告)日：1995-07-20
申请号：DE68923055
申请日：1989-07-08
Applicant: IBM
Inventor： BRANTLEY WILLIAM CAIN , GROH WAYNE STEPHEN , JACKSON RORY DANA , NORTON VERN ALAN
Abstract: Packet switch protocol and circuitry for implementing it are disclosed. According to this protocol, a message transmitter of a first node in the network may send data through a data transmission link at a predetermined rate until it is signalled, via a control signal generated by a message receiver in a second node, to suspend its transmissions. The message transmitter may also be signalled to resume transmitting data. The message receiver includes a buffer memory in which messages are temporarily stored if their selected path is blocked as they pass through the network. When the amount of available space in the buffer is less than a preprogrammed threshold value, the message receiver generates the control signal to suspend message transmission. This threshold value leaves sufficient space in the buffer to store any data which may be in the pipeline between the transmitter and the receiver. When the amount of available space rises above this threshold, the message receiver indicates to the transmitter to resume transmission. A message spanning an interface during transmission may be suspended without losing spatial contiguousness. The message transmitter also transmits a signal which marks the last portion of a message. This signal is stored in the buffer with the message data and is used to delimit messages in the buffer, allowing multiple messages to be stored in one buffer without extra delimiting values.
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公开(公告)号：DE68921365D1
公开(公告)日：1995-04-06
申请号：DE68921365
申请日：1989-03-22
Applicant: IBM
IPC: G06F15/167 , G06F12/12 , G06F13/16 , G06F15/173 , H04L12/56 , G06F15/16 , G06F12/02 , G06F9/46
Abstract: An interconnection network management architecture for use with a large shared memory multiprocessor computing system including a plurality of processors and a plurality of separately addressable main memory modules. Two parallel, interconnection networks are provided each capable of interconnecting any processor to any memory module, and each having different latency characteristics. A Hot-Spot detection means is associated with each main memory module for detecting when a particular address in that module has become a Hot Spot and includes a first memory for storing all detected Hot Spots. A diverter element is associated with each processor for selectively routing memory requests over either said first or second memory network con tingent on its status as a Hot Spot. A second memory is included in each diverter element for storing all Hot Spots detected by the detector elements. A control mechanism determines if any current main memory address is a listed Hot Spot within said second memory and, if so, causes the main memory reference to be transmitted to the memory system over a selected interconnection network. Another component of this mechanism determines if a particular address has been accessed a sufficient number of times within a given timeframe to be deemed a Hot Spot and removes Hot Spots from both the first and second memories when necessary.
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公开(公告)号：DE68923055T2
公开(公告)日：1995-12-21
申请号：DE68923055
申请日：1989-07-08
Applicant: IBM
Inventor： BRANTLEY WILLIAM CAIN , GROH WAYNE STEPHEN , JACKSON RORY DANA , NORTON VERN ALAN
Abstract: Packet switch protocol and circuitry for implementing it are disclosed. According to this protocol, a message transmitter of a first node in the network may send data through a data transmission link at a predetermined rate until it is signalled, via a control signal generated by a message receiver in a second node, to suspend its transmissions. The message transmitter may also be signalled to resume transmitting data. The message receiver includes a buffer memory in which messages are temporarily stored if their selected path is blocked as they pass through the network. When the amount of available space in the buffer is less than a preprogrammed threshold value, the message receiver generates the control signal to suspend message transmission. This threshold value leaves sufficient space in the buffer to store any data which may be in the pipeline between the transmitter and the receiver. When the amount of available space rises above this threshold, the message receiver indicates to the transmitter to resume transmission. A message spanning an interface during transmission may be suspended without losing spatial contiguousness. The message transmitter also transmits a signal which marks the last portion of a message. This signal is stored in the buffer with the message data and is used to delimit messages in the buffer, allowing multiple messages to be stored in one buffer without extra delimiting values.
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Patent Agency Ranking
公开(公告)号：DE3854035D1
公开(公告)日：1995-07-27
申请号：DE3854035
申请日：1988-09-15
Applicant: IBM
Inventor： MCAULIFFE KEVIN PATRIK , MELTON EVELYN AU , NORTON VERN ALAN , PFISTER GREGORY FRANCIS , WAKEFIELD SCOTT PHILIP
Abstract: An aperiodic mapping procedure for the mapping of logical to physical addresses is defined as a permutation function for generating optimized stride accesses in an interleaved multiple device system such as a large, parallel processing shared memory system wherein the function comprises a bit-matrix multiplication of a presented first (logical) address with a predetermined matrix to produce a second (physical) address. The permutation function maps the address from a first to a second address space for improved memory performance in such an interleaved memory system. Assuming that the memory has n logical address bits and 2 separately accessible memory devices (where d
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公开(公告)号：DE3586389T2
公开(公告)日：1993-03-04
申请号：DE3586389
申请日：1985-10-17
Applicant: IBM
Inventor： BRANTLEY JR , MCAULIFEE KEVIN PATRICK , NORTON VERN ALAN , PFISTER GREGORY FRANCIS , WEISS JOSEPH
Abstract: Method and Apparatus for dynamically partitioning a storage system into a global storage efficiently accessible by a number of processors connected to a network, and local storage efficiently accessible by individual processors, including means for interleaving storage references by a processor; means under the control of each processor for controlling the means for interleaving storage references and means for dynamically directing storage references to first or second portions of storage.In operation, a virtual address from a processor is stored in VAR 242 and comprises a segment and/or page index (S/P 1) 244, a page offset (PO) 246 and word offset (WO) 248. The S/P I is used in a conventional way as an index into the storage mapping tables 270 to provide a real address which is placed in register 250. Unique to this disclosure, the table look-up also provides a quantity, the interleave amount, which indicates whether the real address is in local or global storage and, which in the latter event, is used to derive the absolute addresses. The low order bits of the real address may be hashed using Remap 252 to introduce a random element into a sequence of consecutive addresses. The real address after mapping, excluding the word offset (WO) is passed to right rotate device 256 which is controlled by the interleave amount. The width of the field to be rotated and the amount the field is to be rotated are specified by the interleave amount. The derived absolute addresses are entered in register 258 and are passed for use onto a communication network interconnecting the processors and the storage system.
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公开(公告)号：DE3854035T2
公开(公告)日：1996-02-29
申请号：DE3854035
申请日：1988-09-15
Applicant: IBM
Inventor： MCAULIFFE KEVIN PATRIK , MELTON EVELYN AU , NORTON VERN ALAN , PFISTER GREGORY FRANCIS , WAKEFIELD SCOTT PHILIP
Abstract: An aperiodic mapping procedure for the mapping of logical to physical addresses is defined as a permutation function for generating optimized stride accesses in an interleaved multiple device system such as a large, parallel processing shared memory system wherein the function comprises a bit-matrix multiplication of a presented first (logical) address with a predetermined matrix to produce a second (physical) address. The permutation function maps the address from a first to a second address space for improved memory performance in such an interleaved memory system. Assuming that the memory has n logical address bits and 2 separately accessible memory devices (where d
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公开(公告)号：DE3586389D1
公开(公告)日：1992-08-27
申请号：DE3586389
申请日：1985-10-17
Applicant: IBM
Inventor： BRANTLEY JR , MCAULIFEE KEVIN PATRICK , NORTON VERN ALAN , PFISTER GREGORY FRANCIS , WEISS JOSEPH
Abstract: Method and Apparatus for dynamically partitioning a storage system into a global storage efficiently accessible by a number of processors connected to a network, and local storage efficiently accessible by individual processors, including means for interleaving storage references by a processor; means under the control of each processor for controlling the means for interleaving storage references and means for dynamically directing storage references to first or second portions of storage.In operation, a virtual address from a processor is stored in VAR 242 and comprises a segment and/or page index (S/P 1) 244, a page offset (PO) 246 and word offset (WO) 248. The S/P I is used in a conventional way as an index into the storage mapping tables 270 to provide a real address which is placed in register 250. Unique to this disclosure, the table look-up also provides a quantity, the interleave amount, which indicates whether the real address is in local or global storage and, which in the latter event, is used to derive the absolute addresses. The low order bits of the real address may be hashed using Remap 252 to introduce a random element into a sequence of consecutive addresses. The real address after mapping, excluding the word offset (WO) is passed to right rotate device 256 which is controlled by the interleave amount. The width of the field to be rotated and the amount the field is to be rotated are specified by the interleave amount. The derived absolute addresses are entered in register 258 and are passed for use onto a communication network interconnecting the processors and the storage system.
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公开(公告)号：PH25478A
公开(公告)日：1991-07-01
申请号：PH32816
申请日：1985-08-20
Applicant: IBM
Inventor： BRANTLEY WILLIAM CAIN , NORTON VERN ALAN , PFISTER GREGORY FRANCIS , WEISS KEVIN PATRICK JOSEPH NMN
Abstract: Method and Apparatus for dynamically partitioning a storage system into a global storage efficiently accessible by a number of processors connected to a network, and local storage efficiently accessible by individual processors, including means for interleaving storage references by a processor; means under the control of each processor for controlling the means for interleaving storage references and means for dynamically directing storage references to first or second portions of storage.In operation, a virtual address from a processor is stored in VAR 242 and comprises a segment and/or page index (S/P 1) 244, a page offset (PO) 246 and word offset (WO) 248. The S/P I is used in a conventional way as an index into the storage mapping tables 270 to provide a real address which is placed in register 250. Unique to this disclosure, the table look-up also provides a quantity, the interleave amount, which indicates whether the real address is in local or global storage and, which in the latter event, is used to derive the absolute addresses. The low order bits of the real address may be hashed using Remap 252 to introduce a random element into a sequence of consecutive addresses. The real address after mapping, excluding the word offset (WO) is passed to right rotate device 256 which is controlled by the interleave amount. The width of the field to be rotated and the amount the field is to be rotated are specified by the interleave amount. The derived absolute addresses are entered in register 258 and are passed for use onto a communication network interconnecting the processors and the storage system.
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