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公开(公告)号：JP2002305535A
公开(公告)日：2002-10-18
申请号：JP2001386626
申请日：2001-12-19
Applicant: IBM
Inventor： FRAZIER GILES ROGER , PFISTER GREGORY FRANCIS , RECIO RENATO JOHN
Abstract: PROBLEM TO BE SOLVED: To provide a method, apparatus and computer implemented instructions for transferring data. SOLUTION: A request is sent by a requester to a responder. The request includes the amount of available processing space at the requester. When the request is received from the responder, data are identified using the request. The data are placed into a plurality of subsequences of data packets for transfer to the requester, wherein each packet within the set of subsequences hold data in the amount less than or equal to the amount of available space. These subsequences are then sent to the requester one subsequence at a time. A new subsequence is sent each time the available processing space at the requester becomes free to process data from another subsequence.
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2.发明专利
公开(公告)号：JP2003216592A
公开(公告)日：2003-07-31
申请号：JP2002275672
申请日：2002-09-20
Applicant: IBM
Inventor： ARNDT RICHARD LOUIS , CRADDOCK DAVID F , GREGG THOMAS A , JUDD IAN DAVID , PFISTER GREGORY FRANCIS , RECIO RENATO JOHN , DONALD WILLIAM SCHMIDT
Abstract: PROBLEM TO BE SOLVED: To provide some optimizing techniques for sending a work request from a consumer to a channel adapter hardware, and method, device and program for sending a work completion to the consumer. SOLUTION: A distributed computing system having host and I/O end nodes, switches, routers and links interconnecting these components is provided. The end nodes use a pair of transmission/reception queues to transmit/receive messages. The end nodes use completion queues to inform the end user when messages have been completely sent or received and whether an error occurred during the message transmission or reception process. A mechanism for controlling the transfer of the work requests from the consumer to the channel adapter hardware by using only head pointers in the hardware is described. COPYRIGHT: (C)2003,JPO
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公开(公告)号：CA2532777C
公开(公告)日：2010-11-23
申请号：CA2532777
申请日：2004-08-04
Applicant: IBM
Inventor： ELKO DAVID ARLEN , LEPORE DANIEL , MEHTA CHETAN , PFISTER GREGORY FRANCIS , SUGRUE PATRICK JOHN
IPC: H04L12/24
Abstract: A method, system, and product in a data processing system are disclosed for providing centralized management of an InfiniBand distributed system-area network that includes multiple end nodes. A manager application is established in one of the end nodes. An agent application is established in one or more end nodes. Each agent application is independent from the manager application. The manager application maintains a current list of active agent applications and uses the list to manage the agent applications in the end nodes.
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公开(公告)号：CA2532777A1
公开(公告)日：2005-02-24
申请号：CA2532777
申请日：2004-08-04
Applicant: IBM
Inventor： LEPORE DANIEL , ELKO DAVID ARLEN , MEHTA CHETAN , SUGRUE PATRICK JOHN , PFISTER GREGORY FRANCIS
IPC: H04L12/24
Abstract: A method, system, and product in a data processing system are disclosed for providing centralized management of an InfiniBand distributed system-area network that includes multiple end nodes. A manager application is establish ed in one of the end nodes. An agent application is established in one or more end nodes. Each agent application is independent from the manager applicatio n. The manager application maintains a current list of active agent application s and uses the list to manage the agent applications in the end nodes.
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公开(公告)号：DE68921365T2
公开(公告)日：1995-10-05
申请号：DE68921365
申请日：1989-03-22
Applicant: IBM
IPC: G06F15/167 , G06F12/12 , G06F13/16 , G06F15/173 , H04L12/56 , G06F15/16 , G06F12/02 , G06F9/46
Abstract: An interconnection network management architecture for use with a large shared memory multiprocessor computing system including a plurality of processors and a plurality of separately addressable main memory modules. Two parallel, interconnection networks are provided each capable of interconnecting any processor to any memory module, and each having different latency characteristics. A Hot-Spot detection means is associated with each main memory module for detecting when a particular address in that module has become a Hot Spot and includes a first memory for storing all detected Hot Spots. A diverter element is associated with each processor for selectively routing memory requests over either said first or second memory network con tingent on its status as a Hot Spot. A second memory is included in each diverter element for storing all Hot Spots detected by the detector elements. A control mechanism determines if any current main memory address is a listed Hot Spot within said second memory and, if so, causes the main memory reference to be transmitted to the memory system over a selected interconnection network. Another component of this mechanism determines if a particular address has been accessed a sufficient number of times within a given timeframe to be deemed a Hot Spot and removes Hot Spots from both the first and second memories when necessary.
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Patent Agency Ranking
公开(公告)号：DE68921365D1
公开(公告)日：1995-04-06
申请号：DE68921365
申请日：1989-03-22
Applicant: IBM
IPC: G06F15/167 , G06F12/12 , G06F13/16 , G06F15/173 , H04L12/56 , G06F15/16 , G06F12/02 , G06F9/46
Abstract: An interconnection network management architecture for use with a large shared memory multiprocessor computing system including a plurality of processors and a plurality of separately addressable main memory modules. Two parallel, interconnection networks are provided each capable of interconnecting any processor to any memory module, and each having different latency characteristics. A Hot-Spot detection means is associated with each main memory module for detecting when a particular address in that module has become a Hot Spot and includes a first memory for storing all detected Hot Spots. A diverter element is associated with each processor for selectively routing memory requests over either said first or second memory network con tingent on its status as a Hot Spot. A second memory is included in each diverter element for storing all Hot Spots detected by the detector elements. A control mechanism determines if any current main memory address is a listed Hot Spot within said second memory and, if so, causes the main memory reference to be transmitted to the memory system over a selected interconnection network. Another component of this mechanism determines if a particular address has been accessed a sufficient number of times within a given timeframe to be deemed a Hot Spot and removes Hot Spots from both the first and second memories when necessary.
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公开(公告)号：DE3854035D1
公开(公告)日：1995-07-27
申请号：DE3854035
申请日：1988-09-15
Applicant: IBM
Inventor： MCAULIFFE KEVIN PATRIK , MELTON EVELYN AU , NORTON VERN ALAN , PFISTER GREGORY FRANCIS , WAKEFIELD SCOTT PHILIP
Abstract: An aperiodic mapping procedure for the mapping of logical to physical addresses is defined as a permutation function for generating optimized stride accesses in an interleaved multiple device system such as a large, parallel processing shared memory system wherein the function comprises a bit-matrix multiplication of a presented first (logical) address with a predetermined matrix to produce a second (physical) address. The permutation function maps the address from a first to a second address space for improved memory performance in such an interleaved memory system. Assuming that the memory has n logical address bits and 2 separately accessible memory devices (where d
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公开(公告)号：DE3586389T2
公开(公告)日：1993-03-04
申请号：DE3586389
申请日：1985-10-17
Applicant: IBM
Inventor： BRANTLEY JR , MCAULIFEE KEVIN PATRICK , NORTON VERN ALAN , PFISTER GREGORY FRANCIS , WEISS JOSEPH
Abstract: Method and Apparatus for dynamically partitioning a storage system into a global storage efficiently accessible by a number of processors connected to a network, and local storage efficiently accessible by individual processors, including means for interleaving storage references by a processor; means under the control of each processor for controlling the means for interleaving storage references and means for dynamically directing storage references to first or second portions of storage.In operation, a virtual address from a processor is stored in VAR 242 and comprises a segment and/or page index (S/P 1) 244, a page offset (PO) 246 and word offset (WO) 248. The S/P I is used in a conventional way as an index into the storage mapping tables 270 to provide a real address which is placed in register 250. Unique to this disclosure, the table look-up also provides a quantity, the interleave amount, which indicates whether the real address is in local or global storage and, which in the latter event, is used to derive the absolute addresses. The low order bits of the real address may be hashed using Remap 252 to introduce a random element into a sequence of consecutive addresses. The real address after mapping, excluding the word offset (WO) is passed to right rotate device 256 which is controlled by the interleave amount. The width of the field to be rotated and the amount the field is to be rotated are specified by the interleave amount. The derived absolute addresses are entered in register 258 and are passed for use onto a communication network interconnecting the processors and the storage system.
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公开(公告)号：IN166397B
公开(公告)日：1990-04-28
申请号：IN838MA1985
申请日：1985-10-24
Applicant: IBM
Inventor： BRANTLEY WILLIAM CAIN JR , MCAULIFEE KEVIN PATRICK , MORTON VERN ALAN , PFISTER GREGORY FRANCIS , WEISS JOSEPH
Abstract: Method and Apparatus for dynamically partitioning a storage system into a global storage efficiently accessible by a number of processors connected to a network, and local storage efficiently accessible by individual processors, including means for interleaving storage references by a processor; means under the control of each processor for controlling the means for interleaving storage references and means for dynamically directing storage references to first or second portions of storage.In operation, a virtual address from a processor is stored in VAR 242 and comprises a segment and/or page index (S/P 1) 244, a page offset (PO) 246 and word offset (WO) 248. The S/P I is used in a conventional way as an index into the storage mapping tables 270 to provide a real address which is placed in register 250. Unique to this disclosure, the table look-up also provides a quantity, the interleave amount, which indicates whether the real address is in local or global storage and, which in the latter event, is used to derive the absolute addresses. The low order bits of the real address may be hashed using Remap 252 to introduce a random element into a sequence of consecutive addresses. The real address after mapping, excluding the word offset (WO) is passed to right rotate device 256 which is controlled by the interleave amount. The width of the field to be rotated and the amount the field is to be rotated are specified by the interleave amount. The derived absolute addresses are entered in register 258 and are passed for use onto a communication network interconnecting the processors and the storage system.
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公开(公告)号：AT343277T
公开(公告)日：2006-11-15
申请号：AT04742012
申请日：2004-08-04
Applicant: IBM
Inventor： ELKO DAVID ARLEN , LEPORE DANIEL , MEHTA CHETAN , PFISTER GREGORY FRANCIS , SUGRUE PATRICK JOHN
IPC: H04L12/24
Abstract: A method, system, and product in a data processing system are disclosed for providing centralized management of an INFINIBAND distributed system-area network that includes multiple end nodes. A manager application is established in one of the end nodes. An agent application is established in one or more end nodes. Each agent application is independent from the manager application. The manager application maintains a current list of active agent applications and uses the list to manage the agent applications in the end nodes.
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