公开(公告)号：EP1792346A4

公开(公告)日：2009-09-09

申请号：EP05805693

申请日：2005-09-19

Applicant: IBM

Inventor： ANDERSON BRENT A ,  LANZEROTTI LOUIS D ,  NOWAK EDWARD J

IPC: H01L29/737 ,  H01L21/32 ,  H01L21/3213 ,  H01L21/324 ,  H01L29/739 ,  H01L29/76

CPC classification number: H01L29/0653 ,  H01L21/8213 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: A field effect transistor and method of fabricating the field effect transistor. The field effect transistor, including: a gate electrode formed on a top surface of a gate dielectric layer, the gate dielectric layer on a top surface of a single-crystal silicon channel region, the single-crystal silicon channel region on a top surface of a Ge including layer, the Ge including layer on a top surface of a single-crystal silicon substrate, the Ge including layer between a first dielectric layer and a second dielectric layer on the top surface of the single-crystal silicon substrate.

公开(公告)号：EP1502308A4

公开(公告)日：2009-03-18

申请号：EP02734064

申请日：2002-04-26

Applicant: IBM

Inventor： JOHNSON ROBB ALLEN ,  LANZEROTTI LOUIS D

IPC: H01L21/331 ,  H01L29/10 ,  H01L29/737 ,  H01L31/0328

CPC classification number: H01L29/66242 ,  H01L29/1004 ,  H01L29/7378

Abstract: A bipolar transistor for a small signal amplifier that has improved Early voltages, and hence enhanced cutoff frequency. The SiGe layer (14) has a thickness (t) and a Ge content that is greater than the stability limit. The misfit dislocations do not create appreciable charge trapping sites, and do not extend into the overlying base/collector junction, such that performance is improved without yield degradation.

公开(公告)号：EP1488462A4

公开(公告)日：2008-04-23

申请号：EP03719421

申请日：2003-03-19

Applicant: IBM

Inventor： CLARK WILLIAM F ,  FRIED DAVID M ,  LANZEROTTI LOUIS D ,  NOWAK EDWARD J

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/786 ,  H01L29/78 ,  H01L33/00

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/78603 ,  H01L29/78687

Abstract: A structure for a transistor that includes an insulator (10) and a silicon structure on the insulator. The silicon structure includes a central portion (155) and Fins (250) extending from ends of the central portion. A first gate (50) is positioned on a first side of the central portion of the silicon structure. A strain-producing layer (11) could be between the first gate (50) and the first side of the central portion (155) of the silicon structure and a second gate (160) is on a second side of the central portion (155) of the silicon structure.

公开(公告)号：JP2002368147A

公开(公告)日：2002-12-20

申请号：JP2002101203

申请日：2002-04-03

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： COOLBAUGH DOUGLAS D ,  LANZEROTTI LOUIS D ,  MALINOWSKI JOHN C

IPC: H01L29/73 ,  G03F9/00 ,  H01L21/265 ,  H01L21/266 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L23/544 ,  H01L27/06

CPC classification number: G03F9/708 ,  G03F9/7084 ,  H01L21/8249 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a BiCMOS device comprising a deep sub-collector region and a self-aligning mark. SOLUTION: There are provided a step (a) where a layer with a first pattern comprising a thick dielectric material is formed on the surface of a material stack formed on a semiconductor substrate through lithography, a step (b) where high energy/high dose injection is performed via an opening of the first layer as well as the material stack to form at least one deep sub-collector region in the semiconductor substrate, a step (c) where a layer with a second pattern (photoresist or dielectrics) is formed by lithography, and a step (d) where etching is performed through the material stack for forming an alignment mark in the semiconductor substrate, which is positioned below, using the layer with the first pattern as an alignment mark mask.

Abstract translation: 要解决的问题：提供一种用于形成包括深子集电极区域和自对准标记的BiCMOS器件的方法。 解决方案：提供了一种步骤（a），其中通过光刻在形成在半导体衬底上的材料堆叠的表面上形成具有包括厚电介质材料的第一图案的层，步骤（b），其中高能量​​/高剂量 通过第一层的开口以及材料堆叠进行注入以在半导体衬底中形成至少一个深的亚极集电极区域;步骤（c），其中形成具有第二图案的层（光致抗蚀剂或电介质） 以及步骤（d），其中使用具有第一图案的层作为对准标记掩模，通过材料堆叠进行蚀刻以在位于下方的半导体衬底中形成对准标记。

公开(公告)号：JP2004193575A

公开(公告)日：2004-07-08

申请号：JP2003380487

申请日：2003-11-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NATZLE WESLEY C ,  AHLGREN DAVID C ,  BARBEE STEVEN G ,  CANTELL MARC W ,  JAGANNATHAN BASANTH ,  LANZEROTTI LOUIS D ,  SUBBANNA SESHARDI ,  RYAN W WOOTHRICH

IPC: H01L21/302 ,  H01L21/311 ,  H01L21/331 ,  H01L21/8249 ,  H01L29/732

CPC classification number: H01L29/66242 ,  H01L21/31116 ,  H01L21/8249

Abstract: PROBLEM TO BE SOLVED: To provide an oxide etching process that can be used for manufacturing the emitter and base in a bipolar SiGe device. SOLUTION: The low-temperature process used gives electric insulation between the emitters and bases by COR (chemical oxide removal) etching protecting the insulating TEOS (tetraethylorthosilicate) glass 22. The insulating TEOS glass 22 brings about the capacitance reduction, and promotes to achieve high-speed. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2002313798A

公开(公告)日：2002-10-25

申请号：JP2002052091

申请日：2002-02-27

Applicant: IBM

Inventor： DUNN JAMES S ,  HARAME DAVID L ,  JOHNSON JEFFREY B ,  ROBB A JOHNSON ,  LANZEROTTI LOUIS D ,  ST ONGE STEPHEN A

IPC: H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L29/737

Abstract: PROBLEM TO BE SOLVED: To provide an epitaxial base bipolar transistor which has low base resistance and whose capacitance does not increase. SOLUTION: This epitaxial base bipolar transistor is provided with an epitaxial silicon layer on a single crystal semiconductor substrate 54, a raised emitter 64 on the surface of the semiconductor substrate, a raised extrinsic base 58e on the surface of the semiconductor substrate, an insulator 66 as a spacer between the raised emitter and raised extrinsic base, and a diffusion from the raised emitter and from the raised extrinsic base to provide an emitter diffusion and an extrinsic base diffusion in the semiconductor substrate. The emitter diffusion has an emitter diffusion junction depth, and the raised emitter extends to the surface of the semiconductor substrate and the raised extrinsic base extends to the surface of the semiconductor substrate. A difference of height between the surfaces of the emitter and base is less than 20% of the emitter diffusion junction depth.

公开(公告)号：JP2003068754A

公开(公告)日：2003-03-07

申请号：JP2002193698

申请日：2002-07-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： LANZEROTTI LOUIS D ,  VOLDMAN STEVEN H

IPC: H01L21/331 ,  H01L29/08 ,  H01L29/737

CPC classification number: H01L29/66242 ,  H01L29/0821 ,  H01L29/7378

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor bipolar transistor structure which is improved in anti-electrostatic discharge (ESD), and to provide a manufacturing method thereof. SOLUTION: This semiconductor structure includes a bipolar transistor comprising an intrinsic base of a low impurity concentration, a high impurity concentration external base which is adjacent to the intrinsic base and has a doping transition boundary between the high impurity concentration base and the low impurity concentration base, and whose doping transition boundary between the high impurity concentration base and the low impurity concentration base is decided by the end of a window, and a silicide region extending onto the external base, containing the silicide region totally away from the window.

Abstract translation: 要解决的问题：提供一种改进了抗静电放电（ESD）的半导体双极晶体管结构，并提供其制造方法。 解决方案：该半导体结构包括双极晶体管，其包括低杂质浓度的本征基极，与本征基极相邻的高杂质浓度外部基极，并且在高杂质浓度基底与低杂质浓度基底之间具有掺杂跃迁边界 并且其高杂质浓度基极与低杂质浓度基底之间的掺杂跃迁边界由窗口末端决定，并且硅化物区域延伸到外部基底上，其中硅化物区域完全远离窗口。

公开(公告)号：WO03001584A8

公开(公告)日：2004-05-27

申请号：PCT/US0219789

申请日：2002-06-19

Applicant: IBM

Inventor： JAGANNATHAN BASANTH ,  JENG SHWU-JEN ,  JOHNSON JEFFREY B ,  JOHNSON ROBB A ,  LANZEROTTI LOUIS D ,  STEIN KENNETH J ,  SUBBANNA SESHADRI

IPC: H01L21/331 ,  H01L21/8249 ,  H01L29/737 ,  H01L31/11

CPC classification number: H01L29/66242 ,  H01L21/8249 ,  H01L29/7378

Abstract: A method for making a non-self-aligned, heterojunction bipolar transistor includes forming extrinsic base regions (70) with a PFET source/drain implant aligned with the polysilicon in an emitter stack but which are not directly aligned with an emitter opening defined in that stack. This is achieved by making the emitter pedestal (66) wider than the emitter opening. This advantageously removes the dependency of alignment between the extrinsic base regions and the emitter opening, thereby resulting in fewer process steps, reduced thermal cycles, and improved speed.

Abstract translation: 一种用于制造非自对准的异质结双极晶体管的方法包括：在发射极堆叠中形成具有与多晶硅对准的PFET源极/漏极注入的非本征基极区域（70），但并不直接对准在该区域中限定的发射极开口 叠加。 这通过使发射器基座（66）比发射器开口更宽来实现。 这有利地消除了非本征基区和发射极开口之间的对准的依赖性，从而导致更少的工艺步骤，减少的热循环和改进的速度。

公开(公告)号：WO2006034189A3

公开(公告)日：2006-05-04

申请号：PCT/US2005033472

申请日：2005-09-19

Applicant: IBM ,  ANDERSON BRENT A ,  LANZEROTTI LOUIS D ,  NOWAK EDWARD J

Inventor： ANDERSON BRENT A ,  LANZEROTTI LOUIS D ,  NOWAK EDWARD J

IPC: H01L29/737 ,  H01L21/32 ,  H01L21/3213 ,  H01L21/324 ,  H01L29/739 ,  H01L29/76

CPC classification number: H01L29/0653 ,  H01L21/8213 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: A field effect transistor (100) and method of fabricating the field effect transistor. The field effect transistor, including: a gate electrode (165) formed on a top surface (170) of a gate dielectric layer (155), the gate dielectric layer on a top surface (160) of a single-crystal silicon channel region (110), the single-crystal silicon channel region on a top surface of a Ge including layer (135), the Ge including layer on a top surface of a single-crystal silicon substrate (150), the Ge including layer between a first dielectric layer (215A) and a second dielectric layer (215B) on the top surface of the single-crystal silicon substrate.

Abstract translation: 场效应晶体管（100）和制造该场效应晶体管的方法。 该场效应晶体管包括：形成在栅极电介质层（155）的顶表面（170）上的栅电极（165），单晶硅沟道区（155）的顶表面（160）上的栅电介质层 110），在包括Ge的层（135）的顶表面上的单晶硅沟道区，在单晶硅衬底（150）的顶表面上的包含Ge的层，在第一电介质 在所述单晶硅衬底的顶表面上的第一电介质层（215A）和第二电介质层（215B）。

公开(公告)号：AU2003223306A1

公开(公告)日：2003-10-08

申请号：AU2003223306

申请日：2003-03-19

Applicant: IBM

Inventor： CLARK WILLIAM F ,  FRIED DAVID M ,  LANZEROTTI LOUIS D ,  NOWAK EDWARD J

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/786

Abstract: A method and structure for a transistor that includes an insulator and a silicon structure on the insulator. The silicon structure includes a central portion and Fins extending from ends of the central portion. A first gate is positioned on a first side of the central portion of the silicon structure. A strain-producing layer could be between the first gate and the first side of the central portion of the silicon structure and a second gate is on a second side of the central portion of the silicon structure.