公开(公告)号：JP2013105953A

公开(公告)日：2013-05-30

申请号：JP2011249892

申请日：2011-11-15

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

Inventor： SAKUMA KATSUYUKI ,  OBARA SAYURI ,  SUEOKA KUNIAKI ,  TORIYAMA KAZUSHIGE

IPC: H01L25/065 ,  B23K1/00 ,  B23K3/00 ,  B23K3/06 ,  B23K101/40 ,  H01L21/60 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L24/11 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14505 ,  H01L2224/16105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16507 ,  H01L2224/17517 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/8181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2224/48

Abstract: PROBLEM TO BE SOLVED: To provide alignment with high accuracy having affinity with processes of three-dimensional packaging.SOLUTION: In combination of a plurality of studs (40) for regulating relative motions of a plurality of silicon chips in a lateral direction when solder bumps melt between the plurality of silicon chips, according to pitches of a plurality of solder bumps (10) to be arranged between the plurality of silicon chips, positions in the lateral direction are determined by using the positions of the solder bumps in the lateral direction as reference, and the plurality of studs (40) are provided at one silicon chip and the other silicon chip so that motions are relatively regulated when the plurality of silicon chips relatively move in the lateral direction, and positions between the plurality of solder bumps in the lateral direction set for each of the plurality of silicon chips are aligned (in a height direction).

Abstract translation: 要解决的问题：提供具有与三维包装方法的亲和性的高精度对准。 解决方案：结合多个螺柱（40），用于当多个硅芯片之间的焊料凸起熔化时，根据多个焊料凸块的间距（...），调节多个硅芯片在横向上的相对运动 10）布置在多个硅芯片之间，横向方向上的位置通过使用焊料凸块在横向方向上的位置作为参考来确定，并且多个螺柱（40）设置在一个硅芯片上，并且 其它硅芯片，使得当多个硅芯片在横向方向上相对移动时，运动相对调节，并且为多个硅芯片中的每一个设置的横向方向上的多个焊料凸块之间的位置对准（在高度方向 ）。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2013115135A

公开(公告)日：2013-06-10

申请号：JP2011258013

申请日：2011-11-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

Inventor： SAKUMA KATSUYUKI ,  TORIYAMA KAZUSHIGE ,  SUEOKA KUNIAKI ,  OBARA SAYURI

IPC: H01L21/60

CPC classification number: H01L24/81 ,  H01L2924/15787 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To realize high-precision alignment expected between a plurality of chips or between a substrate and chips.SOLUTION: A combination of a plurality of studs is created for regulating relative movement of a plurality of chips in a lateral direction in the case where a solder bump is melted between the plurality of chips. For each of the plurality of chips, the combination of the plurality of studs having a predetermined width is created at a position where any solder bump is defined as a reference in the arrangement of a plurality of solder bumps disposed between the plurality of chips in accordance with a pitch of the plurality of solder bumps in such a manner that the plurality of solder bumps set to each of the plurality of chips are aligned within a predetermined range by regulating the relative movement of the plurality of chips even in the case where the plurality of chips are moved relatively to each other by melting of the plurality of solder bumps.

Abstract translation: 要解决的问题：实现在多个芯片之间或在基板和芯片之间预期的高精度对准。 解决方案：在多个芯片之间熔化焊料凸块的情况下，产生多个螺柱的组合以调节多个芯片在横向方向上的相对运动。 对于多个芯片中的每一个，在具有预定宽度的多个螺柱的组合中产生一个位置，在这样一个位置处，在根据设置在多个芯片之间的多个焊料凸块的布置中将焊料凸点定义为基准 以多个焊料凸块的间距，使得设置为多个芯片中的每一个的多个焊料凸块通过调节多个芯片的相对移动而在预定范围内对准，即使在多个芯片中的多个 芯片通过多个焊料凸块的熔化相对移动。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2013105951A

公开(公告)日：2013-05-30

申请号：JP2011249848

申请日：2011-11-15

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

Inventor： SAKUMA KATSUYUKI ,  TORIYAMA KAZUSHIGE ,  OBARA SAYURI

IPC: H01L21/60

Abstract: PROBLEM TO BE SOLVED: To attain solder bump connection with low stress so as to reduce stress to be applied on a silicon chip even in structure that a low-k material with low (fragile) mechanical strength is used for an interlayer insulation film of the silicon chip.SOLUTION: A square silicon chip (with thickness of 725 μm) and a laminate layer (with thickness of 1000 μm) are connected with each other by hardening after melting of a plurality of two-dimensionally arranged solder bumps between the square silicon chip and the laminate layer via a low-k layer (insulation layer of a wiring layer (BEOL)) which is arranged on the square silicon chip, and as a laminate, a plurality of partial solder bumps arranged from the circumference of the square silicon chip (equivalent to its four sides) to the inside to predetermined rate are adjusted by putting fillers to them so that degrees of elasticity become relatively lower than those of plurality of solder bumps at other parts.

Abstract translation: 要解决的问题：为了获得具有低应力的焊料凸块连接，以便减少施加在硅芯片上的应力，即使在具有低（脆性）机械强度的低k材料用于层间绝缘的结构 硅片片。 解决方案：在正方形硅之间的多个二维排列的焊料凸块熔化之后，通过硬化将一个方形硅芯片（厚度为725μm）和层叠层（厚度为1000μm）彼此连接在一起 芯片和层叠层经由布置在方形硅芯片上的低k层（布线层（BEOL）的绝缘层）形成，并且作为层叠体，从方形硅的圆周排列的多个部分焊料凸块 通过向其内部填充填充物来调节内部到相对于预定速率的芯片（相当于其四边），使得其他部分的弹性程度相对低于多个焊料凸块。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2013156656A

公开(公告)日：2013-08-15

申请号：JP2013086308

申请日：2013-04-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

Inventor： TAIRA YOICHI ,  OBARA SAYURI ,  JEAN HEROUX

IPC: G02B6/122

CPC classification number: G02B6/125 ,  G02B2006/1219

Abstract: PROBLEM TO BE SOLVED: To reduce the amount of optical loss at six planes of a core intersection space (typically having a rectangular parallelepiped shape) formed by intersection of a plurality of optical waveguide cores.SOLUTION: In an intersection structure comprising a plurality of cores 2 and a clad 3 that surrounds the cores 2, the same material as that of the cores 2 is added to two planes, i.e., upper and lower planes, of intersection spaces where the plurality of cores 2 intersect (instead of using a clad material). In an alternative intersection structure comprising cores 2 and a clad 3, four planes that divide (isolate) the intersection spaces where the plurality of cores 2 intersect, that is, four discontinuity spaces 6 between the core intersection space and the cores connected thereto, are filled with the same material as that of the clad 3 (instead of using a core material so as to be connected seamlessly).

Abstract translation: 要解决的问题：减少由多个光波导芯相交形成的芯交叉部分（通常具有长方体形状）的六个平面处的光损耗量。解决方案：在包括多个核心的交叉结构 2和围绕芯2的包层3，将与芯2相同的材料添加到多个芯2相交的交叉空间的两个平面即上平面和下平面（而不是使用包层材料 ）。 在包含芯2和包层3的替代交叉结构中，划分（隔离）多个芯2相交的交叉空间的四个平面，即，在核心交叉空间和与其连接的芯之间的四个不连续空间6是 填充与包层3相同的材料（而不是使用芯材料以便无缝连接）。

公开(公告)号：JP2001228478A

公开(公告)日：2001-08-24

申请号：JP2001002426

申请日：2001-01-10

Applicant: IBM

Inventor： FUKUZAWA TADASHI ,  OBARA SAYURI ,  LEE VICTOR YEE WAY ,  MILLER ROBERT D ,  SCOTT JOHN CAMPBELL ,  SWANSON SALLY A

IPC: G02F1/061 ,  G02F1/1335 ,  G02F1/13357

Abstract: PROBLEM TO BE SOLVED: To provide a full color liquid crystal display using a photoluminescence(PL) fiber. SOLUTION: New architecture simplifies an LCD manufacture process by substituting a photolithography step for color filter manufacture to a fiber spinning technique at low cost and with high throughput. The new LCD architecture has the power efficiency higher than a conventional LCD. Following structures are included in the three structures of the LCD device using a photoluminescence(PL) fiber array. The first structure having the PL fiber array located behind an LC shutter (to a user), the second structure having the PL fiber array located on the LC shutter, and the third structure where the PL fiber array in located in an LC cell outside. In one of the structures of these, the fiber not only emits light, but performs the polarization of incident light.