公开(公告)号：EP1695383A4

公开(公告)日：2007-12-12

申请号：EP03819162

申请日：2003-12-16

Applicant: IBM

Inventor： HE ZHONG-XIANG ,  JOSEPH J ALVIN ,  ORNER A BRADLEY ,  RAMACHANDRAN VIDHYA ,  ST ONGE A STEPHEN ,  WANG PING-CHUAN

IPC: H01L21/8249 ,  H01L21/768 ,  H01L23/485 ,  H01L23/538 ,  H01L27/06

CPC classification number: H01L21/76838 ,  H01L21/76802 ,  H01L21/8249 ,  H01L23/485 ,  H01L23/5389 ,  H01L27/0623 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors (116) and a plurality of vertical bipolar transistors (118) positioned on a single substrate (110). The vertical bipolar transistors (118) are taller devices than the CMOS transistors (116). In this structure, a passivating layer (112) is positioned above the substrate (110), and between the vertical bipolar transistors (118) and the CMOS transistors (116). A wiring layer (120) is above the passivating layer (112). The vertical bipolar transistors (118) are in direct contact with the wiring layer (120) and the CMOS transistors (116) are connected to the wiring layer (114) by contacts extending through the passivating layer (112).

公开(公告)号：AU2003300962A1

公开(公告)日：2005-07-14

申请号：AU2003300962

申请日：2003-12-16

Applicant: IBM

Inventor： WANG PING-CHUAN ,  HE ZHONG-XIANG ,  JOSEPH J ALVIN ,  ORNER A BRADLEY ,  RAMACHANDRAN VIDHYA ,  ONGE A STEPHEN ST

IPC: H01L21/768 ,  H01L21/8249 ,  H01L23/485 ,  H01L23/538 ,  H01L27/06 ,  H01L23/48 ,  H01L29/06

Abstract: Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors and a plurality of vertical bipolar transistors positioned on a single substrate. The vertical bipolar transistors are taller devices than the CMOS transistors. In this structure, a passivating layer is positioned above the substrate, and between the vertical bipolar transistors and the CMOS transistors. A wiring layer is above the passivating layer. The vertical bipolar transistors are in direct contact with the wiring layer and the CMOS transistors are connected to the wiring layer by contacts extending through the passivating layer.