公开(公告)号：EP1671358A4

公开(公告)日：2009-10-21

申请号：EP04789450

申请日：2004-09-30

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  GAMBINO JEFFREY P ,  HE ZHONG-XIANG ,  RAMACHANDRAN VIDHYA

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/768 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L21/7687 ,  H01L23/5223 ,  H01L23/53238 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1695383A4

公开(公告)日：2007-12-12

申请号：EP03819162

申请日：2003-12-16

Applicant: IBM

Inventor： HE ZHONG-XIANG ,  JOSEPH J ALVIN ,  ORNER A BRADLEY ,  RAMACHANDRAN VIDHYA ,  ST ONGE A STEPHEN ,  WANG PING-CHUAN

IPC: H01L21/8249 ,  H01L21/768 ,  H01L23/485 ,  H01L23/538 ,  H01L27/06

CPC classification number: H01L21/76838 ,  H01L21/76802 ,  H01L21/8249 ,  H01L23/485 ,  H01L23/5389 ,  H01L27/0623 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors (116) and a plurality of vertical bipolar transistors (118) positioned on a single substrate (110). The vertical bipolar transistors (118) are taller devices than the CMOS transistors (116). In this structure, a passivating layer (112) is positioned above the substrate (110), and between the vertical bipolar transistors (118) and the CMOS transistors (116). A wiring layer (120) is above the passivating layer (112). The vertical bipolar transistors (118) are in direct contact with the wiring layer (120) and the CMOS transistors (116) are connected to the wiring layer (114) by contacts extending through the passivating layer (112).

公开(公告)号：EP1792343A4

公开(公告)日：2009-11-11

申请号：EP05754954

申请日：2005-05-26

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  FEILCHENFELD NATALIE ,  GAUTSCH MICHAEL L ,  HE ZHONG-XIANG ,  MOON MATTHEW D ,  RAMACHANDRAN VIDHYA ,  WATERHOUSE BARBARA

IPC: H01L21/8242 ,  H01L21/02 ,  H01L21/20 ,  H01L23/522 ,  H01L27/01 ,  H01L27/08

CPC classification number: H01L23/5223 ,  H01L27/016 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  Y10T29/49002 ,  H01L2924/00

公开(公告)号：EP1794778A4

公开(公告)日：2009-06-03

申请号：EP05779566

申请日：2005-08-04

Applicant: IBM

Inventor： CHINTHAKINDI ANIL K ,  COOLBAUGH DOUGLAS D ,  RAMACHANDRAN VIDHYA ,  RASSEL ROBERT M

IPC: H01L21/20

CPC classification number: H01L28/24 ,  H01L27/0629 ,  H01L29/7833

Abstract: A FEOL/MEOL metal resistor (32) that has tight sheet resistance tolerance (on the order of about 5% or less), high current density (on the order of about 0.5 mA/micron or greater), lower parasitics than diffused resistors and lower TCR than standard BEOL metal resistors as well as various methods of integrating such a metal resistor structure (32) into a CMOS technology are provided.

公开(公告)号：WO02069368A3

公开(公告)日：2002-11-21

申请号：PCT/GB0200758

申请日：2002-02-20

Applicant: IBM ,  IBM UK

Inventor： WANG PING-CHUAN ,  EDWARDS ROBERT DANIEL ,  MALINOWSKI JOHN ,  RAMACHANDRAN VIDHYA ,  KALDOR STEFFEN

IPC: H01L21/312 ,  H01L21/314 ,  H01L21/768 ,  H01L23/31 ,  H01L23/532 ,  H01L23/64

CPC classification number: H01L21/02134 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02282 ,  H01L21/3124 ,  H01L21/3144 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/3192 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: A structure/method for reducing the stress between a dielectric, passivation layer and a metallic structure comprising coating the metallic structure with a low stress modulus buffer material, and forming the dielectric passivation layer covering the low stress modulus buffer material. The low stress modulus buffer material is composed of a layer of a polymeric material selected from at least one of the group consisting of a hydrogen/alkane SQ (SilsesQuioxane) resin, polyimide, and a polymer resin. The dielectric, passivation layer is composed of at least one layer of a material selected from at least one of the group consisting of silicon oxide and silicon nitride. A protective layer is formed over the dielectric, passivation layer. The low stress modulus buffer material has a thermal coefficient of expansion between that of the metallic structure and that of the dielectric passivation layer. In particular, the dielectric passivation layer between the metallic structure and the low stress modulus buffer material has a thermal coefficient of expansion between about 5ppm/ DEG C and about 20ppm/ DEG C.

Abstract translation: 一种用于减小电介质，钝化层和金属结构之间的应力的结构/方法，包括用低应力模量缓冲材料涂覆金属结构，以及形成覆盖低应力模量缓冲材料的电介质钝化层。 低应力模量缓冲材料由选自氢/烷烃SQ（SilsesQuioxane）树脂，聚酰亚胺和聚合物树脂中的至少一种的聚合材料层组成。 电介质钝化层由至少一层选自氧化硅和氮化硅中的至少一种的材料组成。 在电介质钝化层上形成保护层。 低应力模量缓冲材料具有在金属结构和介电钝化层的热膨胀系数之间的热膨胀系数。 特别地，金属结构和低应力模量缓冲材料之间的介电钝化层的热膨胀系数为约5ppm /℃至约20ppm /℃。

公开(公告)号：WO2006017600A3

公开(公告)日：2006-06-22

申请号：PCT/US2005027618

申请日：2005-08-04

Applicant: IBM ,  CHINTHAKINDI ANIL K ,  COOLBAUGH DOUGLAS D ,  RAMACHANDRAN VIDHYA ,  RASSEL ROBERT M

Inventor： CHINTHAKINDI ANIL K ,  COOLBAUGH DOUGLAS D ,  RAMACHANDRAN VIDHYA ,  RASSEL ROBERT M

IPC: H01L21/20

CPC classification number: H01L28/24 ,  H01L27/0629 ,  H01L29/7833

Abstract: A FEOL/MEOL metal resistor (32) that has tight sheet resistance tolerance (on the order of about 5% or less), high current density (on the order of about 0.5 mA/micron or greater), lower parasitics than diffused resistors and lower TCR than standard BEOL metal resistors as well as various methods of integrating such a metal resistor structure (32) into a CMOS technology are provided.

Abstract translation: FEOL / MEOL金属电阻（32）具有紧密的薄层电阻公差（约5％或更小），高电流密度（约0.5mA /微米或更大），比扩散电阻器更低的寄生效应， 提供比标准BEOL金属电阻器更低的TCR以及将这种金属电阻器结构（32）集成到CMOS技术中的各种方法。

公开(公告)号：WO2005122245A2

公开(公告)日：2005-12-22

申请号：PCT/US2005018521

申请日：2005-05-26

Applicant: IBM ,  COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  FEILCHENFELD NATALIE ,  GAUTSCH MICHAEL L ,  HE ZHONG-XIANG ,  MOON MATTHEW D ,  RAMACHANDRAN VIDHYA ,  WATERHOUSE BARBARA

Inventor： COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  FEILCHENFELD NATALIE ,  GAUTSCH MICHAEL L ,  HE ZHONG-XIANG ,  MOON MATTHEW D ,  RAMACHANDRAN VIDHYA ,  WATERHOUSE BARBARA

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/8242 ,  H01L27/01 ,  H01L27/08

CPC classification number: H01L23/5223 ,  H01L27/016 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  Y10T29/49002 ,  H01L2924/00

Abstract: Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer (102, 106) is formed above a lower conductor layer (100) and an upper conductor layer (104, 108) is formed above the dielectric layer. The invention then forms an etch stop layer (200) above the upper conductor layer and the dielectric layer, and forms a hardmask (202) (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist (300) is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.

Abstract translation: 公开了一种制造金属 - 绝缘体 - 金属（MIM）电容器的方法。 在该方法中，在下导体层（100）的上方形成介电层（102,106），在电介质层的上方形成上导体层（104,108）。 然后，本发明在上导体层和电介质层之上形成蚀刻停止层（200），并在蚀刻停止层上形成硬掩模（202）（氧化硅硬掩模，氮化硅硬掩模等）。 接下来，在硬掩模上图案化光致抗蚀剂（300），其允许通过光刻胶蚀刻硬掩模，蚀刻停止层，电介质层和下导体层。

公开(公告)号：WO2005034201A3

公开(公告)日：2007-12-06

申请号：PCT/US2004032405

申请日：2004-09-30

Applicant: IBM ,  COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  GAMBINO JEFFREY P ,  HE ZHONG-XIANG ,  RAMACHANDRAN VIDHYA

Inventor： COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  GAMBINO JEFFREY P ,  HE ZHONG-XIANG ,  RAMACHANDRAN VIDHYA

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/768 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L21/7687 ,  H01L23/5223 ,  H01L23/53238 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for a MIM capacitor, the structure including: an electronic device, comprising: an interievel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interievel dielectric layer, atop surface of the bottom electrode co-planer with a top surface of the interievel dielectric layer; a conductive diffusion barrier in direct contact with the top surface of the bottom electrode; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric. The conductive diffusion barrier may be recessed into the copper bottom electrode or an additional recessed conductive diffusion barrier provided. Compatible resistor and alignment mark structures are also disclosed.

Abstract translation: 一种MIM电容器的方法和结构，所述结构包括：电子器件，包括：形成在半导体衬底上的电介质层; 形成在所述层间电介质层中的铜底电极，所述底电极共平面的顶表面具有所述电介质层的顶表面; 与底部电极的顶表面直接接触的导电扩散阻挡层; 与所述导电扩散阻挡层的顶表面直接接触的MIM电介质; 以及与MIM电介质的顶表面直接接触的顶部电极。 导电扩散阻挡层可以凹进到铜底电极或设置的另外的凹入的导电扩散阻挡层中。 还公开了兼容的电阻器和对准标记结构。

公开(公告)号：AU2003300962A1

公开(公告)日：2005-07-14

申请号：AU2003300962

申请日：2003-12-16

Applicant: IBM

Inventor： WANG PING-CHUAN ,  HE ZHONG-XIANG ,  JOSEPH J ALVIN ,  ORNER A BRADLEY ,  RAMACHANDRAN VIDHYA ,  ONGE A STEPHEN ST

IPC: H01L21/768 ,  H01L21/8249 ,  H01L23/485 ,  H01L23/538 ,  H01L27/06 ,  H01L23/48 ,  H01L29/06

Abstract: Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors and a plurality of vertical bipolar transistors positioned on a single substrate. The vertical bipolar transistors are taller devices than the CMOS transistors. In this structure, a passivating layer is positioned above the substrate, and between the vertical bipolar transistors and the CMOS transistors. A wiring layer is above the passivating layer. The vertical bipolar transistors are in direct contact with the wiring layer and the CMOS transistors are connected to the wiring layer by contacts extending through the passivating layer.

公开(公告)号：AU2002232005A1

公开(公告)日：2002-09-12

申请号：AU2002232005

申请日：2002-02-20

Applicant: IBM

Inventor： WANG PING-CHUAN ,  RAMACHANDRAN VIDHYA ,  EDWARDS ROBERT DANIEL ,  MALINOWSKI JOHN ,  KALDOR STEFFEN

IPC: H01L21/312 ,  H01L21/314 ,  H01L21/768 ,  H01L23/31 ,  H01L23/532 ,  H01L23/64

Abstract: A structure/method for reducing the stress between a dielectric, passivation layer and a metallic structure comprising coating the metallic structure with a low stress modulus buffer material, and forming the dielectric passivation layer covering the low stress modulus buffer material. The low stress modulus buffer material is composed of a layer of a polymeric material selected from at least one of the group consisting of a hydrogen/alkane SQ (SilsesQuioxane) resin, polyimide, and a polymer resin. The dielectric, passivation layer is composed of at least one layer of a material selected from at least one of the group consisting of silicon oxide and silicon nitride. A protective layer is formed over the dielectric, passivation layer. The low stress modulus buffer material has a thermal coefficient of expansion between that of the metallic structure and that of the dielectric passivation layer. In particular, the dielectric passivation layer between the metallic structure and the low stress modulus buffer material has a thermal coefficient of expansion between about 5 ppm/° C. and about 20 ppm/° C.