公开(公告)号：EP2095409A4

公开(公告)日：2014-05-21

申请号：EP07842115

申请日：2007-09-10

Applicant: IBM

Inventor： YANG CHIH-CHAO ,  WANG PING-CHUAN ,  WANG YUN-YU

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76847 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：WO02069368A3

公开(公告)日：2002-11-21

申请号：PCT/GB0200758

申请日：2002-02-20

Applicant: IBM ,  IBM UK

Inventor： WANG PING-CHUAN ,  EDWARDS ROBERT DANIEL ,  MALINOWSKI JOHN ,  RAMACHANDRAN VIDHYA ,  KALDOR STEFFEN

IPC: H01L21/312 ,  H01L21/314 ,  H01L21/768 ,  H01L23/31 ,  H01L23/532 ,  H01L23/64

CPC classification number: H01L21/02134 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02282 ,  H01L21/3124 ,  H01L21/3144 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/3192 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: A structure/method for reducing the stress between a dielectric, passivation layer and a metallic structure comprising coating the metallic structure with a low stress modulus buffer material, and forming the dielectric passivation layer covering the low stress modulus buffer material. The low stress modulus buffer material is composed of a layer of a polymeric material selected from at least one of the group consisting of a hydrogen/alkane SQ (SilsesQuioxane) resin, polyimide, and a polymer resin. The dielectric, passivation layer is composed of at least one layer of a material selected from at least one of the group consisting of silicon oxide and silicon nitride. A protective layer is formed over the dielectric, passivation layer. The low stress modulus buffer material has a thermal coefficient of expansion between that of the metallic structure and that of the dielectric passivation layer. In particular, the dielectric passivation layer between the metallic structure and the low stress modulus buffer material has a thermal coefficient of expansion between about 5ppm/ DEG C and about 20ppm/ DEG C.

Abstract translation: 一种用于减小电介质，钝化层和金属结构之间的应力的结构/方法，包括用低应力模量缓冲材料涂覆金属结构，以及形成覆盖低应力模量缓冲材料的电介质钝化层。 低应力模量缓冲材料由选自氢/烷烃SQ（SilsesQuioxane）树脂，聚酰亚胺和聚合物树脂中的至少一种的聚合材料层组成。 电介质钝化层由至少一层选自氧化硅和氮化硅中的至少一种的材料组成。 在电介质钝化层上形成保护层。 低应力模量缓冲材料具有在金属结构和介电钝化层的热膨胀系数之间的热膨胀系数。 特别地，金属结构和低应力模量缓冲材料之间的介电钝化层的热膨胀系数为约5ppm /℃至约20ppm /℃。

公开(公告)号：EP2255381A4

公开(公告)日：2012-03-07

申请号：EP09704712

申请日：2009-01-23

Applicant: IBM

Inventor： JOSHI RAJIV V ,  HSU LOIUS LU-CHEN ,  WANG PING-CHUAN ,  YANG ZHIJIAN

IPC: H01L21/337 ,  G11C7/12 ,  G11C11/12 ,  G11C11/404 ,  G11C11/412

CPC classification number: G11C29/04 ,  G11C7/12 ,  G11C11/412

公开(公告)号：EP2286444A4

公开(公告)日：2012-11-21

申请号：EP09747138

申请日：2009-04-28

Applicant: IBM

Inventor： ESHUN EBENEZER E ,  HE ZHONG-XIANG ,  RASSEL ROBERT M ,  COOLBAUGH DOUGLAS ,  GEBRESELASIE EPHREM G ,  WANG PING-CHUAN ,  KIM DEOK-KEE ,  KOTHANDARAMAN CHANDRASEKHARAN ,  ROBSON NORMAN W ,  MOY DAN ,  SAFRAN JOHN M ,  STEIN KENNETH J ,  HO HERBERT L ,  YAN HONGWEN

IPC: H01L23/525 ,  H01L27/06

CPC classification number: H01L27/0629 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1695383A4

公开(公告)日：2007-12-12

申请号：EP03819162

申请日：2003-12-16

Applicant: IBM

Inventor： HE ZHONG-XIANG ,  JOSEPH J ALVIN ,  ORNER A BRADLEY ,  RAMACHANDRAN VIDHYA ,  ST ONGE A STEPHEN ,  WANG PING-CHUAN

IPC: H01L21/8249 ,  H01L21/768 ,  H01L23/485 ,  H01L23/538 ,  H01L27/06

CPC classification number: H01L21/76838 ,  H01L21/76802 ,  H01L21/8249 ,  H01L23/485 ,  H01L23/5389 ,  H01L27/0623 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors (116) and a plurality of vertical bipolar transistors (118) positioned on a single substrate (110). The vertical bipolar transistors (118) are taller devices than the CMOS transistors (116). In this structure, a passivating layer (112) is positioned above the substrate (110), and between the vertical bipolar transistors (118) and the CMOS transistors (116). A wiring layer (120) is above the passivating layer (112). The vertical bipolar transistors (118) are in direct contact with the wiring layer (120) and the CMOS transistors (116) are connected to the wiring layer (114) by contacts extending through the passivating layer (112).

公开(公告)号：JP2011015396A

公开(公告)日：2011-01-20

申请号：JP2010142690

申请日：2010-06-23

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： JOSHI RAJIV VASANT ,  YANG ZHIJIAN ,  GUO JONG-RU ,  WANG PING-CHUAN ,  HSU LOUIS LU-CHEN

IPC: H03K5/08 ,  H01L21/822 ,  H01L27/04 ,  H03F1/52

CPC classification number: H03K17/0822

Abstract: PROBLEM TO BE SOLVED: To provide an apparatus and method for mitigating a leakage current of a semiconductor device before catastrophic leakage current runaway occurs.SOLUTION: A leakage current shift monitor unit 20 is electrically connected to an output node of a leakage current target unit 10 and collects leakage currents from a selected target semiconductor device for two consecutive predefined temporal periods and measures the difference between the collected leakage currents. A comparator 40 receives and compares the outputs of the current shift monitor unit 20 and a reference voltage generator 30. The comparator 40 propagates an alert signal to the leakage current target unit 10 when the leakage voltage output from the leakage current shift monitor unit 20 exceeds the reference voltage, that is, a condition that indicates that the leakage current is about to approach catastrophic runaway levels. This alert signal attains leak mitigation also including a repair voltage to be applied to a gate of the target semiconductor device.

Abstract translation: 要解决的问题：提供一种在灾难性漏电流失控之前减轻半导体器件的漏电流的装置和方法。解决方案：泄漏电流移动监视器单元20电连接到漏电流目标单元10的输出节点 并从所选择的目标半导体器件收集泄漏电流两个连续的预定义时间周期，并测量所收集的漏电流之间的差异。 比较器40接收并比较当前移动监视器单元20和参考电压发生器30的输出。当从泄漏电流移动监视单元20输​​出的泄漏电压超过时，比较器40向泄漏电流目标单元10传播报警信号 参考电压，即表示泄漏电流即将接近灾难性失控水平的条件。 该警报信号还实现泄漏减轻，还包括要施加到目标半导体器件的栅极的修复​​电压。

公开(公告)号：WO2006063170A3

公开(公告)日：2007-01-25

申请号：PCT/US2005044488

申请日：2005-12-08

Applicant: IBM ,  GUARIN FERNANDO ,  HOSTETTER J EDWIN JR ,  RAUCH STEWART E III ,  WANG PING-CHUAN ,  YANG ZHIJIAN J

Inventor： GUARIN FERNANDO ,  HOSTETTER J EDWIN JR ,  RAUCH STEWART E III ,  WANG PING-CHUAN ,  YANG ZHIJIAN J

IPC: H01L21/337 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8238 ,  H01L21/8249 ,  H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC classification number: H01L29/7304 ,  H01L29/7378

Abstract: A method for recovery of degradation caused by avalanche hot carriers is provided that includes subjecting an idle bipolar transistor exhibiting avalanche degradation to a thermal anneal step which increases temperature of the transistor thereby recovering the avalanche degradation of the bipolar transistor. In one embodiment, the annealing source is a self-heating structure that is a Si-containing resistor that is located side by side with an emitter of the bipolar transistor. During the recovering step, the bipolar transistor including the self-heating structure is placed in the idle mode (i.e., without bias) and a current from a separate circuit is flown through the self-heating structure. In another embodiment of the present, the annealing step is a result of providing a high forward current (around the peak fT current or greater) to the bipolar transistor while operating below the avalanche condition (V CB of less than 1 V). Under the above conditions, about 40% or greater of the degradation can be recovered. In yet another embodiment of the present invention, the thermal annealing step may include a rapid thermal anneal (RTA), a furnace anneal, a laser anneal or a spike anneal.

Abstract translation: 提供了一种用于回收由雪崩热载体引起的降解的方法，其包括使表现出雪崩降解的空闲双极晶体管经历热退火步骤，所述热退火步骤增加了晶体管的温度，从而恢复了双极晶体管的雪崩劣化。 在一个实施例中，退火源是自发热结构，其是与双极晶体管的发射极并排放置的含Si电阻器。 在恢复步骤期间，包括自发热结构的双极晶体管被置于空闲模式（即，没有偏压），并且来自单独电路的电流流过自热结构。 在本发明的另一个实施例中，退火步骤是在双极晶体管的周围提供高正向电流（围绕峰值fT电流或更大）的结果，同时在低于雪崩条件（V CB）的情况下运行 超过1 V）。 在上述条件下，可以回收约40％以上的降解。 在本发明的又一实施例中，热退火步骤可以包括快速热退火（RTA），炉退火，激光退火或尖峰退火。

公开(公告)号：JP2011009740A

公开(公告)日：2011-01-13

申请号：JP2010129210

申请日：2010-06-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： WAI-KIN LI ,  WANG PING-CHUAN ,  FILIPPI RONALD G

IPC: H01L21/768 ,  H01L21/3205 ,  H01L23/52

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76847 ,  H01L21/76852 ,  H01L23/5286 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a structure of power grid for supplying electric power to semiconductor devices, and a method of producing the structure.SOLUTION: An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls that are covered with a conductive liner, in which the bottom is formed directly on top of the stud and in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of the via. The method of producing the semiconductor structure is also provided.

Abstract translation: 要解决的问题：提供用于向半导体器件供电的电网结构及其制造方法。本发明的一个实施例提供一种半导体结构，其可以包括第一导电材料柱 形成在介电层内; 第二导电材料的通孔，其具有被导电衬垫覆盖的底部和侧壁，其中底部直接形成在螺柱的顶部上并通过导电衬套与通孔接触; 以及在通孔的侧壁处通过导电衬套连接到通孔的第三导电材料的一个或多个导电路径。 还提供了制造半导体结构的方法。

公开(公告)号：JP2008205458A

公开(公告)日：2008-09-04

申请号：JP2008028398

申请日：2008-02-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： YANG CHIH-CHAO ,  CHANDA KAUSHIK ,  WANG PING-CHUAN

IPC: H01L21/3205 ,  H01L23/52

CPC classification number: H01L21/76849 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76856 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a structure and method of fabricating an interconnect structure with a bi-layer metal cap. SOLUTION: In one embodiment, this method of fabricating an interconnect structure with a bi-layer metal cap includes the steps of: forming an interconnect structure portion in a dielectric material layer; and forming a bi-layer metallic cap on the top surface of an interconnect structure portion. This method also includes the step of depositing the blanket layer of a dielectric capping layer, which covers the exposed surface of the dielectric material layer and the surface of a bi-layer metallic cap. The bi-layer metallic cap comprises: a metal capping layer formed on the conductive surface of an interconnect structure portion; and metal nitride formed on the top portion of the metal capping layer. The interconnect structure comprises: an interconnect structure portion formed in the dielectric layer: a bi-layer metallic cap formed on the top portion of the interconnect structure portion; and a dielectric capping layer formed on the bi-layer metallic cap. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用双层金属帽制造互连结构的结构和方法。 解决方案：在一个实施例中，制造具有双层金属帽的互连结构的这种方法包括以下步骤：在介电材料层中形成互连结构部分; 以及在互连结构部分的顶表面上形成双层金属帽。 该方法还包括沉积介电覆盖层的覆盖层的步骤，该覆盖层覆盖介电材料层的暴露表面和双层金属盖的表面。 双层金属盖包括：形成在互连结构部分的导电表面上的金属覆盖层; 和金属氮化物形成在金属覆盖层的顶部上。 所述互连结构包括：形成在所述电介质层中的互连结构部分：形成在所述互连结构部分的顶部上的双层金属帽; 以及形成在双层金属盖上的电介质覆盖层。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：WO2012134801A3

公开(公告)日：2013-01-03

申请号：PCT/US2012028847

申请日：2012-03-13

Applicant: IBM ,  FILIPPI RONALD G ,  BONILLA GRISELDA ,  CHANDA KAUSHIK ,  GRUNOW STEPHAN ,  LUSTIG NAFTALI E ,  SIMON ANDREW H ,  WANG PING-CHUAN

Inventor： FILIPPI RONALD G ,  BONILLA GRISELDA ,  CHANDA KAUSHIK ,  GRUNOW STEPHAN ,  LUSTIG NAFTALI E ,  SIMON ANDREW H ,  WANG PING-CHUAN

IPC: H01L23/62 ,  H01L21/82

CPC classification number: H01L23/5226 ,  G01R31/025 ,  G01R31/04 ,  G01R31/07 ,  G01R31/327 ,  H01L23/5256 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53295 ,  H01L23/58 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A back end of the line (BEOL) fuse structure having a stack of vias (122, 132). The stacking of vias (122, 132) leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner (124) and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.

Abstract translation: 具有堆叠通孔（122,132）的线（BEOL）熔丝结构的后端。 通孔（122,132）的堆叠导致高的纵横比，使得通孔内的衬里和种子覆盖较差。 衬垫（124）和种子层的弱点导致较高的电迁移（EM）故障概率。 保险丝结构由于衬垫和种子覆盖不良而解决故障。 设计特征允许确定故障发生的位置，确定熔断器编程之后损坏区域的程度，并防止损坏的介质区域的进一步传播。