Ultra-scalable high-speed heterojunction vertical n-channel misfet and its method
    1.
    发明专利
    Ultra-scalable high-speed heterojunction vertical n-channel misfet and its method 有权
    超高可靠性高速异步垂直N沟道MISFET及其方法

    公开(公告)号:JP2005012214A

    公开(公告)日:2005-01-13

    申请号:JP2004175740

    申请日:2004-06-14

    Abstract: PROBLEM TO BE SOLVED: To provide a metal-insulator-semiconductor field effect transistor (MISFET) composed of a conductive channel in which no hetero-barrier exists in the flowing direction of currents and a heterojunction between the source/drain and main body (bulk) of the transistor. SOLUTION: The structures of the strained vertical channel of the field effect transistor in which a drain region, main body region, and source region are incorporated in the side wall of a vertical single-crystal semiconductor structure, the field effect transistor, and a CMOS circuit and the forming methods of the channel, transistor, and circuit are described. The heterojunction is formed between the source and main body of the field effect transistor and the source region and vertical channel independently form lattice strains to the main body region. The drain region contains a carbon-doped region to prevent the diffusion of a dopant (boron) into the main body region. When this invention is used, the problem about the leakage current from the source region due to the heterojunction and lattice strains is reduced. Apart from the leakage current, a lattice strain can be formed in a channel region for increasing mobility by selecting the semiconductor material. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题:为了提供一种金属 - 绝缘体 - 半导体场效应晶体管(MISFET),其由在电流的流动方向上不存在异质势垒的导电沟道和源极/漏极与主体之间的异质结构成 体(体)晶体管。 解决方案:场效应晶体管的应变垂直沟道的结构,其中漏极区域,主体区域和源极区域结合在垂直单晶半导体结构的侧壁中,场效应晶体管, 并描述了CMOS电路和沟道,晶体管和电路的形成方法。 在场效应晶体管的源极和主体之间形成异质结,并且源极区和垂直沟道独立地形成到主体区域的晶格应变。 漏极区域包含碳掺杂区域,以防止掺杂剂(硼)扩散到主体区域中。 当使用本发明时,由于异质结和晶格应变引起的来自源极区的漏电流的问题减少了。 除了漏电流之外,通过选择半导体材料,可以在通道区域中形成晶格应变以增加迁移率。 版权所有(C)2005,JPO&NCIPI

    Low-leakage heterojunction vertical transistor and its high-performance device
    2.
    发明专利
    Low-leakage heterojunction vertical transistor and its high-performance device 有权
    低泄漏异常垂直晶体管及其高性能器件

    公开(公告)号:JP2005012213A

    公开(公告)日:2005-01-13

    申请号:JP2004175642

    申请日:2004-06-14

    Abstract: PROBLEM TO BE SOLVED: To provide an insulated-gate semiconductor field effect transistor (MISFET) composed of a conductive channel in which no hetero-barrier exists in the flowing direction of currents and a heterojunction between the source/drain and main body (bulk) of the transistor. SOLUTION: The structures of the vertical channel 165 of the field effect transistor in which a drain region 162, main body region 163, and source region 164 are incorporated in the side wall of a vertical single-crystal semiconductor structure, the field effect transistor, and a CMOS circuit and the forming methods of the channel, transistor, and circuit are described. The heterojunction is formed between the source and main body of the transistor and the source region 164 and vertical channel 165 independently form lattice stains to the main body region 163. The drain region 162 contains a carbon-doped region to prevent the diffusion of dopants (namely, boron (B) and phosphorus (P)) into the main body region 163. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题:为了提供一种绝缘栅半导体场效应晶体管(MISFET),其由在电流的流动方向上不存在异质势垒的导电沟道和源极/漏极与主体之间的异质结构成 (体积)的晶体管。 解决方案:场效应晶体管的垂直沟道165的结构,其中漏极区162,主体区163和源极区164结合在垂直单晶半导体结构的侧壁中,场 描述了效应晶体管和CMOS电路以及沟道,晶体管和电路的形成方法。 在晶体管的源极和主体之间形成异质结,并且源极区域164和垂直沟道165独立地形成到主体区域163的晶格斑。漏极区域162包含碳掺杂区域以防止掺杂剂的扩散( 即硼(B)和磷(P))进入主体区域163.版权所有(C)2005,JPO&NCIPI

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