Abstract:
PROBLEM TO BE SOLVED: To provide a metal-insulator-semiconductor field effect transistor (MISFET) composed of a conductive channel in which no hetero-barrier exists in the flowing direction of currents and a heterojunction between the source/drain and main body (bulk) of the transistor. SOLUTION: The structures of the strained vertical channel of the field effect transistor in which a drain region, main body region, and source region are incorporated in the side wall of a vertical single-crystal semiconductor structure, the field effect transistor, and a CMOS circuit and the forming methods of the channel, transistor, and circuit are described. The heterojunction is formed between the source and main body of the field effect transistor and the source region and vertical channel independently form lattice strains to the main body region. The drain region contains a carbon-doped region to prevent the diffusion of a dopant (boron) into the main body region. When this invention is used, the problem about the leakage current from the source region due to the heterojunction and lattice strains is reduced. Apart from the leakage current, a lattice strain can be formed in a channel region for increasing mobility by selecting the semiconductor material. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract:
PROBLEM TO BE SOLVED: To provide an insulated-gate semiconductor field effect transistor (MISFET) composed of a conductive channel in which no hetero-barrier exists in the flowing direction of currents and a heterojunction between the source/drain and main body (bulk) of the transistor. SOLUTION: The structures of the vertical channel 165 of the field effect transistor in which a drain region 162, main body region 163, and source region 164 are incorporated in the side wall of a vertical single-crystal semiconductor structure, the field effect transistor, and a CMOS circuit and the forming methods of the channel, transistor, and circuit are described. The heterojunction is formed between the source and main body of the transistor and the source region 164 and vertical channel 165 independently form lattice stains to the main body region 163. The drain region 162 contains a carbon-doped region to prevent the diffusion of dopants (namely, boron (B) and phosphorus (P)) into the main body region 163. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract:
A semiconductor wafer structure for integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate; an electrically conductive back gate layer formed on the lower insulating layer; an upper insulating layer formed on the back gate layer; and a hybrid semiconductor-on-insulator layer formed on the upper insulating layer, the hybrid semiconductor-on-insulator layer comprising a first portion having a first crystal orientation and a second portion having a second crystal orientation.
Abstract:
A semiconductor wafer structure for integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate; an electrically conductive back gate layer formed on the lower insulating layer; an upper insulating layer formed on the back gate layer; and a hybrid semiconductor-on-insulator layer formed on the upper insulating layer, the hybrid semiconductor-on-insulator layer comprising a first portion having a first crystal orientation and a second portion having a second crystal orientation.