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    PERSONAL COMPUTER BUS AND VIDEO ADAPTER FOR HIGH PERFORMANCE PARALLEL INTERFACE
    1.
    发明专利
    PERSONAL COMPUTER BUS AND VIDEO ADAPTER FOR HIGH PERFORMANCE PARALLEL INTERFACE 未知

    公开(公告)号：CA2044835A1

    公开(公告)日：1992-01-26

    申请号：CA2044835

    申请日：1991-06-18

    Applicant: IBM

    Inventor： DETSCHEL WILLIAM F ,  NORTON DARWIN W JR ,  PADDOCK RICHARD C

    IPC: G06F13/38 ,  G06F5/06 ,  G06F13/12 ,  G06F13/00

    Abstract: KI9-90-003 PERSONAL COMPUTER BUS AND VIDEO ADAPTER FOR HIGH PERFORMANCE PARALLEL INTERFACE Adapters attach the bus or video display of a personal computer or workstation to a high performance parallel interface (HIPPI) channel of a host computer. The HIPPI channel operate. at a burst rate of 100 megabytes (MB) per second. The adapter includes an electrical circuit interface to provide compatible signal levels between the HIPPI channel and the bus of the personal computer or workstation. The adapter attaching the bus includes a first-in, first-out (FIFO) buffer that receives data words from the HIPPI channel. Control logic monitors the status of the FIFO buffer and interlocks the operation of the personal computer or workstation bus with the HIPPI channel so that proper data transfer is performed by the FIFO buffer. The adapter attaching the video display includes a pair of buffers operating in a ping-pong fashion to allow data to be written while data is being read. The buffers can be addressed by the personal computer or workstation as if they were internal memory. To allow a plurality of workstations to be connected to a single HIPPI channel, the HIPPI adapter is modified to include a pass through function allowing the devices to be connected in a "Daisy chain".

    2.
    发明专利
    未知

    公开(公告)号：FR2276640A1

    公开(公告)日：1976-01-23

    申请号：FR7516534

    申请日：1975-05-21

    Applicant: IBM

    Inventor： HOLMES ARTHUR W JR ,  OMAN PRICE W ,  PADDOCK RICHARD C ,  PRICE DONALD W

    IPC: G06F9/46 ,  G06F9/38 ,  G06F15/16 ,  G06F15/177 ,  G06F15/80 ,  G06F13/00

    Abstract: A processor including a plurality of synchronized subprocessors, each implemented on an integrated circuit substrate and each having an instruction register and instruction executing circuits for independently executing a portion of the functions required by an instruction being simultaneously executed by each subprocessor. Execution is initiated and synchronized by simultaneously loading the same instruction into each subprocessor.

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