公开(公告)号：CA2074879A1

公开(公告)日：1993-05-01

申请号：CA2074879

申请日：1992-07-29

Applicant: IBM

Inventor： GRUNBOK WARREN W ,  KNOWLES BILLY J ,  MILANI WILLIAM R ,  MORAN DOUGLAS R ,  PONTIUS DALE E ,  PRICE DONALD W ,  TAMLYN ROBERT ,  TING YEE-MING ,  TRAN DE ,  YEH HENRY

IPC: G06F12/06 ,  G06F13/16 ,  G11C8/12 ,  G11C8/00

Abstract: KI9-91-010 MEMORY SYSTEM AND UNIQUE MEMORY CHIP ALLOWING ISLAND INTERLACE A memory system and a unique memory chip is disclosed wherein multiple islands on a chip can be separately accessed by separate island controllers whereby concurrent use of the several islands or arrays on a chip can be achieved.

公开(公告)号：CA1030268A

公开(公告)日：1978-04-25

申请号：CA225415

申请日：1975-04-22

Applicant: IBM

Inventor： HOLMES ARTHUR W JR ,  OMAN PRICE W ,  PADDOCK RICHARD C ,  PRICE DONALD W

IPC: G06F9/46 ,  G06F9/38 ,  G06F15/16 ,  G06F15/177 ,  G06F15/80

Abstract: A processor including a plurality of synchronized subprocessors, each implemented on an integrated circuit substrate and each having an instruction register and instruction executing circuits for independently executing a portion of the functions required by an instruction being simultaneously executed by each subprocessor. Execution is initiated and synchronized by simultaneously loading the same instruction into each subprocessor.

公开(公告)号：CA1023861A

公开(公告)日：1978-01-03

申请号：CA192695

申请日：1974-02-15

Applicant: IBM

Inventor： HOLMES ARTHUR W JR ,  LONG GERALD B ,  PADDOCK RICHARD C ,  PI SHING-CHOU ,  PRICE DONALD W

IPC: G11C17/00 ,  G06F9/26 ,  G11C11/413 ,  G11C17/12

公开(公告)号：BR9203918A

公开(公告)日：1993-05-04

申请号：BR9203918

申请日：1992-10-08

Applicant: IBM

Inventor： GRUNBOK WARREN W ,  KNOWLES BILLY J ,  MILANI WILLIAM R ,  MORAN DOUGLAS R ,  PONTIUS DALE E ,  PRICE DONALD W ,  TAMLYN ROBERT ,  TING YEE-MINE ,  TRAN DE ,  YEH HENRY

IPC: G06F12/06 ,  G06F13/16 ,  G11C8/12 ,  G11C7/00

Abstract: A memory system (15) and a memory chip is disclosed wherein multiple islands (21) on a chip can be separately accessed by separate island controllers whereby concurrent use of the several islands or arrays on a chip can be achieved.

公开(公告)号：FR2276640A1

公开(公告)日：1976-01-23

申请号：FR7516534

申请日：1975-05-21

Applicant: IBM

Inventor： HOLMES ARTHUR W JR ,  OMAN PRICE W ,  PADDOCK RICHARD C ,  PRICE DONALD W

IPC: G06F9/46 ,  G06F9/38 ,  G06F15/16 ,  G06F15/177 ,  G06F15/80 ,  G06F13/00

Abstract: A processor including a plurality of synchronized subprocessors, each implemented on an integrated circuit substrate and each having an instruction register and instruction executing circuits for independently executing a portion of the functions required by an instruction being simultaneously executed by each subprocessor. Execution is initiated and synchronized by simultaneously loading the same instruction into each subprocessor.