公开(公告)号：CA2015214A1

公开(公告)日：1990-11-30

申请号：CA2015214

申请日：1990-04-23

Applicant: IBM

Inventor： BONO RICHARD C ,  BRANDT HENRY R ,  CAVAGNARO HAROLD F ,  LEE ARLIN E ,  NORTON DARWIN W JR ,  SHALKEY ERIC T ,  SILSBEE TERRENCE K ,  WEHRLY DAVID S ,  WILLIAMS CLIFFORD T ,  ZIMMERMAN TERRENCE K

IPC: G06F13/12 ,  G06F13/42 ,  G06F15/17

Abstract: The disclosed arrangement provides apparatus and method for implementing a High Speed Link (HSL) such as the newly proposed ANSI High-Speed Channel (HSC) standard on processors complexes like the IBM 3090 having a paging store with an independent bus. A high speed link adapter (HSLA) including input and output buffers and controls is coupled to the independent bus under program control. Program access to high speed link is obtained by an extension to the Page-in and Page-out instructions.

公开(公告)号：CA2015214C

公开(公告)日：1996-01-02

申请号：CA2015214

申请日：1990-04-23

Applicant: IBM

Inventor： BONO RICHARD C ,  BRANDT HENRY R ,  CAVAGNARO HAROLD F ,  LEE ARLIN E ,  NORTON DARWIN W JR ,  SHALKEY ERIC T ,  SILSBEE DAVID L ,  WEHRLY DAVID S ,  WILLIAMS CLIFFORD T ,  ZIMMERMAN TERRENCE K

IPC: G06F13/12 ,  G06F13/42 ,  G06F15/17 ,  G06F13/00

Abstract: This embodiment provides apparatus and method for implementing a High Speed Link (HSL) such as the newly proposed ANSI High Performance Parallel interface (HPPI) standard on processors complexes like the IBM? 3090TM having a paging store with an independent bus. A high speed link adapter (HSLA) including input and output buffers and controls is coupled to the independent bus under program control. Program access to high speed link is obtained by an extension to the Page-in and Page-out instructions.

公开(公告)号：CA2044835A1

公开(公告)日：1992-01-26

申请号：CA2044835

申请日：1991-06-18

Applicant: IBM

Inventor： DETSCHEL WILLIAM F ,  NORTON DARWIN W JR ,  PADDOCK RICHARD C

IPC: G06F13/38 ,  G06F5/06 ,  G06F13/12 ,  G06F13/00

Abstract: KI9-90-003 PERSONAL COMPUTER BUS AND VIDEO ADAPTER FOR HIGH PERFORMANCE PARALLEL INTERFACE Adapters attach the bus or video display of a personal computer or workstation to a high performance parallel interface (HIPPI) channel of a host computer. The HIPPI channel operate. at a burst rate of 100 megabytes (MB) per second. The adapter includes an electrical circuit interface to provide compatible signal levels between the HIPPI channel and the bus of the personal computer or workstation. The adapter attaching the bus includes a first-in, first-out (FIFO) buffer that receives data words from the HIPPI channel. Control logic monitors the status of the FIFO buffer and interlocks the operation of the personal computer or workstation bus with the HIPPI channel so that proper data transfer is performed by the FIFO buffer. The adapter attaching the video display includes a pair of buffers operating in a ping-pong fashion to allow data to be written while data is being read. The buffers can be addressed by the personal computer or workstation as if they were internal memory. To allow a plurality of workstations to be connected to a single HIPPI channel, the HIPPI adapter is modified to include a pass through function allowing the devices to be connected in a "Daisy chain".