公开(公告)号：WO0229818A3

公开(公告)日：2003-06-19

申请号：PCT/EP0110937

申请日：2001-09-21

Applicant: IBM ,  IBM DEUTSCHLAND

Inventor： HSU LOUIS LU-CHEN ,  PARENT RICHARD MICHAEL ,  WORDEMAN MATTHEW R

IPC: G11C5/14 ,  G11C8/08 ,  G11C11/406 ,  G11C11/4074

CPC classification number: G11C11/406 ,  G11C5/146 ,  G11C8/08 ,  G11C11/4074 ,  G11C2207/104

Abstract: A system and method for considerable reduction of power consumption in memory circuits implementing Vbb (array body bias) and Vwl (negative word line) voltage generators. The system comprises switching off the negative WL generator during sleep or standby mode, so that no power is consumed. A relaxed refresh operation is carried out and the negative WL is powered by the Vbb generator. The noise coupled to the negative WL supply from BL swing is reduced due to the joint Vbb-Vwl decoupling scheme. In the active mode, the Vbb and Vneg are separated to avoid any cross-over noise and to maintain design flexibility. During power-on period, the ramp-up rate of Vbb level is improved by the Vwl generator. The advantages may be summarized as: (1) simpler Vbb generator design, (2) much smaller Vbb generator size, (3) reduced Vbb power, (4) no stand-by current from Vwl generator, (5) low decoupling noise for Vwl level during stand-by or sleep mode, (6) enhanced ramp-up rate for Vbb during power-on, (7) no cross-over noise between Vbb and Vwl during active mode, and (8) design flexibility of Vbb and Vwl in the active mode. The principles and advantages of the invention may be applied to any two or more DC generator systems, negative or positive.

Abstract translation: 用于实现Vbb（阵列体偏置）和Vwl（负字线）电压发生器的存储电路中的功耗的显着降低的系统和方法。 该系统包括在睡眠或待机模式期间关闭负WL发生器，使得不消耗电力。 执行松弛的刷新操作，负的WL由Vbb发生器供电。 由于联合Vbb-Vwl去耦方案，耦合到BL摆幅的负WL电源的噪声减小。 在活动模式下，Vbb和Vneg被分离，以避免任何交叉噪声并保持设计灵活性。 在上电期间，Vwl发生器提高了Vbb电平的上升速率。 其优点可概括为：（1）Vbb发电机设计更简单，（2）Vbb发电机尺寸小得多，（3）Vbb功率降低，（4）Vwl发电机无待机电流，（5）低去耦噪声 待机或休眠模式下的Vwl电平，（6）上电时Vbb的提升速率，（7）活动模式期间Vbb和Vwl之间无交叉噪声，（8）Vbb和Vbb的设计灵活性 Vwl处于活动模式。 本发明的原理和优点可以应用于任何两个或多个DC发电机系统，负极或正极。

公开(公告)号：DE10196673T1

公开(公告)日：2003-08-28

申请号：DE10196673

申请日：2001-09-21

Applicant: IBM

Inventor： HSU LOUIS LU-CHEN ,  PARENT RICHARD MICHAEL ,  WORDEMAN MATTHEW R

IPC: G11C5/14 ,  G11C8/08 ,  G11C11/406 ,  G11C11/4074

Abstract: A system and method for considerable reduction of power consumption in memory circuits implementing Vbb (array body bias) and Vwl (negative word line) voltage generators. The system comprises switching off the negative WL generator during sleep or standby mode, so that no power is consumed. A relaxed refresh operation is carried out and the negative WL is powered by the Vbb generator. The noise coupled to the negative WL supply from BL swing is reduced due to the joint Vbb-Vwl decoupling scheme. In the active mode, the Vbb and Vneg are separated to avoid any cross-over noise and to maintain design flexibility. During power-on period, the ramp-up rate of Vbb level is improved by the Vwl generator. The advantages may be summarized as: (1) simpler Vbb generator design, (2) much smaller Vbb generator size, (3) reduced Vbb power, (4) no stand-by current from Vwl generator, (5) low decoupling noise for Vwl level during stand-by or sleep mode, (6) enhanced ramp-up rate for Vbb during power-on, (7) no cross-over noise between Vbb and Vwl during active mode, and (8) design flexibility of Vbb and Vwl in the active mode. The principles and advantages of the invention may be applied to any two or more DC generator systems, negative or positive.

公开(公告)号：DE10196673B4

公开(公告)日：2008-01-31

申请号：DE10196673

申请日：2001-09-21

Applicant: IBM

Inventor： HSU LOUIS LU-CHEN ,  PARENT RICHARD MICHAEL ,  WORDEMAN MATTHEW R

IPC: G11C8/08 ,  G11C5/14 ,  G11C11/406 ,  G11C11/4074

Abstract: A system and method for considerable reduction of power consumption in memory circuits implementing Vbb (array body bias) and Vwl (negative word line) voltage generators. The system comprises switching off the negative WL generator during sleep or standby mode, so that no power is consumed. A relaxed refresh operation is carried out and the negative WL is powered by the Vbb generator. The noise coupled to the negative WL supply from BL swing is reduced due to the joint Vbb-Vwl decoupling scheme. In the active mode, the Vbb and Vneg are separated to avoid any cross-over noise and to maintain design flexibility. During power-on period, the ramp-up rate of Vbb level is improved by the Vwl generator. The advantages may be summarized as: (1) simpler Vbb generator design, (2) much smaller Vbb generator size, (3) reduced Vbb power, (4) no stand-by current from Vwl generator, (5) low decoupling noise for Vwl level during stand-by or sleep mode, (6) enhanced ramp-up rate for Vbb during power-on, (7) no cross-over noise between Vbb and Vwl during active mode, and (8) design flexibility of Vbb and Vwl in the active mode. The principles and advantages of the invention may be applied to any two or more DC generator systems, negative or positive.

公开(公告)号：AU8990501A

公开(公告)日：2002-04-15

申请号：AU8990501

申请日：2001-09-21

Applicant: IBM

Inventor： PARENT RICHARD MICHAEL ,  WORDEMAN MATTHEW R

IPC: G11C5/14 ,  G11C8/08 ,  G11C11/406 ,  G11C11/4074

Abstract: A system and method for considerable reduction of power consumption in memory circuits implementing Vbb (array body bias) and Vwl (negative word line) voltage generators. The system comprises switching off the negative WL generator during sleep or standby mode, so that no power is consumed. A relaxed refresh operation is carried out and the negative WL is powered by the Vbb generator. The noise coupled to the negative WL supply from BL swing is reduced due to the joint Vbb-Vwl decoupling scheme. In the active mode, the Vbb and Vneg are separated to avoid any cross-over noise and to maintain design flexibility. During power-on period, the ramp-up rate of Vbb level is improved by the Vwl generator. The advantages may be summarized as: (1) simpler Vbb generator design, (2) much smaller Vbb generator size, (3) reduced Vbb power, (4) no stand-by current from Vwl generator, (5) low decoupling noise for Vwl level during stand-by or sleep mode, (6) enhanced ramp-up rate for Vbb during power-on, (7) no cross-over noise between Vbb and Vwl during active mode, and (8) design flexibility of Vbb and Vwl in the active mode. The principles and advantages of the invention may be applied to any two or more DC generator systems, negative or positive.