公开(公告)号：JP2002009612A

公开(公告)日：2002-01-11

申请号：JP2001136609

申请日：2001-05-07

Applicant: IBM

Inventor： DHONG SANG HOO ,  NGO HUNG CAI ,  PARK JAEHONG ,  OSAMU TAKAHASHI

IPC: H01L21/82 ,  H03K19/173

Abstract: PROBLEM TO BE SOLVED: To provide a method and a device for mounting dynamic logic having a dynamic programmable logic gate. SOLUTION: The method and the device activate so as to complement a programmable logic array(PLA) used for a high-speed microprocessor design. A matrix, consisting of selectable cells permits powerful logic functions such as AND-OR gate functions with a minimum possible number of entries and of transistors(TRs). Employing the programmable logic array and a dynamic programmable gate can considerably improve the efficiency of logic blocks almost, without the need for adding of the circuit region.

公开(公告)号：DE10038491B4

公开(公告)日：2004-05-19

申请号：DE10038491

申请日：2000-08-08

Applicant: IBM

Inventor： DHONG SANG HOO ,  NGO HUNG CAI ,  PARK JAEHONG

IPC: G06F7/02 ,  G06F12/08

公开(公告)号：DE10038491A1

公开(公告)日：2001-04-19

申请号：DE10038491

申请日：2000-08-08

Applicant: IBM

Inventor： DHONG SANG HOO ,  NGO HUNG CAI ,  PARK JAEHONG

IPC: G06F7/02 ,  G06F12/08

Abstract: The comparator has a first transistor stage (101), to which numbers (A,B) are input. A second transistor stage (102) receives the output of the first transistor stage (101), and outputs specific values which are input to a third transistor stage (103) which outputs values (GT,EQ,LT) corresponding to 'greater-than', 'equality' and 'less-than' output values. The output values are calculated according to a series of claimed formulae. Independent claims are also included for the following: (a) Cache memory; (b) Integrated circuit