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公开(公告)号：BR9203093A
公开(公告)日：1994-03-01
申请号：BR9203093
申请日：1992-08-10
Applicant: IBM
Inventor： FARRELL JOSEPH K , GORDON JEFFREY S , JENNESS ROBERT V , KHHL DANIEL C , LEE TIMOTHY V , PARKER TONY E
Abstract: Disclosed is an arrangement for "seamlessly" integrating telephone services relative to primitive analog telephone equipment into general purpose computer systems. The integration is effected through present "secondary" adaptation of data link control adapter devices which are adapted primarily for coupling such computer systems to high speed data communication links for transmission and reception of digital data. This permits general resources of the computer system (keyboard, memory, disk drives, etc.) to be used for specific applications associated with telephone services. Presently described link control devices have a telephone attachment port which couples through analog-to-digital conversion circuits to a primitive analog telephone (no dial or keys). Such devices operate normally in time division multiplex to process communication data between a computer (host) system and data link ports. The present adaptation includes a host programmable time division switch circuit within the control device, which can be conditioned dynamically to route digitized telephone signals directly between its data link and telephone ports, whereby telephone signals can be transmitted isochronally between a local user of the host system and a remote telephone, over a telephone network connection, while data signals are being transferred in either direction between the host system and equipment at the remote telephone station over the same connection.
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公开(公告)号：CA2034031C
公开(公告)日：1994-04-05
申请号：CA2034031
申请日：1991-01-11
Applicant: IBM
Inventor： FARRELL JOSEPH K , GORDON JEFFREY S , KUHL DANIEL C , LEE TIMOTHY V , PARKER TONY E
Abstract: BURST TIME DIVISION MULTIPLEX INTERFACE FOR INTEGRATED DATA LINK CONTROLLER Subject burst time division multiplex interface connects circuits which perform "layer 1 (L1)" line control functions relative to a data communication network with devices which perform "Layer 2 (L2)" link control functions relative to the same network (L1 and L2 defined by OSI Specifications of the International Standards Organization). The interface is characterized by presentation of bursts of readiness indicating pulses from the L1 circuit to the L2 device during each basic time division multiplex time slot. The pulses indicate readiness of the circuits for data bit exchange, and separate time overlapped bursts are sent to indicate readiness of the circuit to send and receive data bits. Each burst contains a varied number of pulses ranging from O to n (where n is greater than 2, and in the disclosed embodiment equals 8). The bursts are positioned in a womdpw of time occupying a fraction of the slot interval close to the emd of each slot. This allows the L2 device to perform state swapping operations during the remainder of the slot to prepare for burst exchanges with different network channels to which the slots are allocatable ant to be able to devote maximum processing time to performance of L2 tasks required relative to the channels. The channels operate under various communication protocols (HDLC, LAP-D, clear/voice, etc.). Slot time spacings are variable by the L1 circuits to adjust to signalling conditions in the network.
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Patent Agency Ranking
公开(公告)号：CA2035673A1
公开(公告)日：1991-09-16
申请号：CA2035673
申请日：1991-02-05
Applicant: IBM
Inventor： FARRELL JOSEPH K , GORDON JEFFREY S , JENNESS ROBERT V , KUHL DANIEL C , LEE TIMOTHY V , PARKER TONY E
Abstract: A single chip integrated data link control (IDLC) device provides full duplex data throughput and versatile protocol adaptation between variably configured time channels on a high speed TDM digital link (e.g. T-1 or T-3 line) and a host data processing system. The device can handle multiple channels of voice and varied protocol data traffic, and thereby is suited for use in primary rate ISDN (Integrated Services Digital Network) applications. Synchronous and asynchronous special purpose logic sections in the device respectively interface with the network and a bus extending to external processing systems. Logic in the synchronous section forms plural-stage receive and transmit processing pipelines relative to the network interface. A "resource manager" element (RSM) and time swap (TS) RAM memory operate to dynamically vary states in these pipelines in synchronism with channel time slots at the network interface, whereby each pipeline operates in multitasking mode to perform plural functions relative to each channel during each time slot. The device also includes integrated memory queues in which communication data and channel status information are stacked relative to the device interfaces. Capacities and modes of operation of these queues are selected to minimize effects on chip size, throughput and cost, while supporting operations in the synchronous section pipelines so that critical time dependencies between consecutive pipeline stages, and between the pipelines and external processors, are lessened.
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公开(公告)号：CA2034031A1
公开(公告)日：1991-09-16
申请号：CA2034031
申请日：1991-01-11
Applicant: IBM
Inventor： FARRELL JOSEPH K , GORDON JEFFREY S , KUHL DANIEL C , LEE TIMOTHY V , PARKER TONY E
Abstract: Subject burst time division multiplex interface connects circuits which perform "layer 1 (L1)" line control functions relative to a data communication network with devices which perform "Layer 2 (L2)" link control functions relative to the same network (L1 and L2 defined by OSI Specifications of the International Standards Organisation). The interface is characterised by presentation of bursts of readiness indicating pulses from the L1 circuit to the L2 device during each basic time division multiplex time slot. The pulses indicate readiness of the circuits for data bit exchange, and separate time overlapped bursts are sent to indicate readiness of the circuits to send and receive data bits. Each burst contains a varied number of pulses ranging from 0 to n (where n is greater than 2, and in the disclosed embodiment equals 8). The bursts are positioned in a window of time occupying a fraction of the slot interval close to the end of each slot. This allows the L2 device to perform state swapping operations during the remainder of the slot to prepare for burst exchanges with different network channels to which the slots are allocatable and to be able to devote maximum processing time to performance of L2 tasks required relative to the channels. The channels operate under various communication protocols (HDLC, LAP-D, clear/voice, etc.). Slot time spacings are variable by the L1 circuits to adjust to signalling conditions in the network.
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公开(公告)号：CA2035696C
公开(公告)日：1995-04-18
申请号：CA2035696
申请日：1991-02-05
Applicant: IBM
Inventor： FARRELL JOSEPH K , GORDON JEFFREY S , KUHL DANIEL C , LEE TIMOTHY V , PARKER TONY E
Abstract: An improved data link control device for use in high speed data communication applications, for instance primary rate ISDN applications, includes facilities for dynamic HyperChannel mapping. In such mapping, plural communication channels which ordinarily could be used for separate communication applications are associated as a HyperChannel group, and data communication is carried out concurrently over all channels of the group so as to advantageously utilize the aggregate bandwidth of the group. The present mapping facilities comprise means for designating one channel in each mapped group as a reference channel for the group, means for associating all other channels in the group to the respective reference channel, means for storing control information relative to the respective reference channel, and means responsive to the control information for conducting a data communication operation through all of the grouped channels including the reference channel as if all of said channels constituted a single extended channel having a bandwidth equal to that of the reference channel multiplied by the number of channels in the group.
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公开(公告)号：CA2035673C
公开(公告)日：1994-04-19
申请号：CA2035673
申请日：1991-02-05
Applicant: IBM
Inventor： FARRELL JOSEPH K , GORDON JEFFREY S , JENNESS ROBERT V , KUHL DANIEL C , LEE TIMOTHY V , PARKER TONY E
Abstract: INTEGRATED DATA LINK CONTROLLER WITH SYNCHRONOUS LINK INTERFACE AND ASYNCHRONOUS HOST PROCESSOR INTERFACE A single chip integrated data link control (IDLC) device provides full duplex data throughput and versatile protocol adaptation between variably configured time channels on a high speed TDM digital link (e.g. T-1 or T-3 line) and a host data processing system. The device can handle multiple channels of voice and varied protocol data traffic, and thereby is suited for use in primary rate ISDN (Integrated Services Digital Network) applications. Synchronous and asynchronous special purpose logic sections in the device respectively interface with the network and a bus extending to external processing systems. Logic in the synchronous section forms plural-stage receive and transmit processing pipelines relative to the network interface. A "resource manager" element (RSM) and time swap (TS) RAM memory operate to dynamically vary states in these pipelines in synchronism with channel time slots at the network interface, whereby each pipeline operates in multitasking mode to perform plural functions relative to each channel during each time slot. The device also includes integrated memory queues in which communication data and channel status information are stacked relative to the device interfaces. Capacities and modes of operation of these queues are selected to minimize effects on chip size, throughput and cost, while supporting operations in the synchronous section pipelines so that critical time dependencies between consecutive pipeline stages, and between the pipelines and external processors, are lessened.
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公开(公告)号：CA1180818A
公开(公告)日：1985-01-08
申请号：CA418005
申请日：1982-12-17
Applicant: IBM
Inventor： MOORE VICTOR S , VENESKI GERARD A , PARKER TONY E , RHODES JOSEPH C JR , KRAFT WAYNE R , STAHL WILLIAM L JR
Abstract: MICROWORD CONTROL SYSTEM UTILIZING MULTIPLEXED PROGRAMMABLE LOGIC ARRAYS A microword control system is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor. This microword control system includes a plurality of programmable logic array mechanisms responsive to the processor instruction to be executed for individually producing different ones of the microwords needed to execute such instruction. This microword control system also includes microword-responsive control circuitry for controlling the operation of the data processor. This microword control system further includes mutliplexing circuitry for supplying microwords from different ones of the programmable logic array mechanisms to the control circuitry during different time intervals.
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