公开(公告)号：WO2011051015A3

公开(公告)日：2011-10-20

申请号：PCT/EP2010062579

申请日：2010-08-27

Applicant: IBM ,  IBM UK ,  WONG KEITH KWONG HON ,  GUO DECHAO ,  KWON UNOH ,  WANG YUN-YU ,  PARKS CHRISTOPHER CARR

Inventor： WONG KEITH KWONG HON ,  GUO DECHAO ,  KWON UNOH ,  WANG YUN-YU ,  PARKS CHRISTOPHER CARR

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/511 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

Abstract: A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided.

Abstract translation: 提供了一种形成p型半导体器件的方法，其在一个实施例中采用含铝阈值电压偏移层来产生朝向p型半导体器件的价带的阈值电压偏移。 形成p型半导体器件的方法可以包括在衬底上形成栅极结构，其中栅极结构包括与衬底接触的栅极介电层，存在于栅极介电层上的含铝阈值电压偏移层， 以及与含铝阈值电压偏移层和栅极电介质层中的至少一个接触的含金属层。 P型源极和漏极区域可以形成在衬底的与其上存在栅极结构的部分相邻的衬底中。 还提供了由上述方法提供的p型半导体器件。

公开(公告)号：MY124349A

公开(公告)日：2006-06-30

申请号：MYPI9905231

申请日：1999-12-02

Applicant: IBM

Inventor： ANDRICACOS PANAYOTIS CONSTANTINOU ,  CABRAL CYRIL JR ,  PARKS CHRISTOPHER CARR ,  RODBELL KENNETH PARKER ,  TSAI ROGER-YEN-LUEN

IPC: H01L21/00 ,  H01L21/265 ,  H01L21/3205 ,  H01L21/283 ,  H01L21/288 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

Abstract: A METHOD FOR FORMING A COPPER CONDUCTOR (56, 58) IN AN ELECTRONIC STRUCTURE (50) BY FIRST DEPOSITING A COPPER COMPOSITION (88, 90, 100) IN A RECEPTACLE FORMED IN THE ELECTRONIC STRUCTURE, AND THEN ADDING IMPURITIES INTO THE COPPER COMPOSITION SUCH THAT ITS ELECTROMIGRATION RESISTANCE IS IMPROVED IS DISCLOSED. IN THE METHOD, THE COPPER COMPOSITION CAN BE DEPOSITED BY A VARIETY OF TECHNIQUES SUCH AS ELECTROPLATING, PHYSICAL VAPOR DEPOSITION AND CHEMICAL VAPOR DEPOSITION. THE IMPURITIES WHICH CAN BE IMPLANTED INCLUDE THOSE OF C, O, CI, S AND N AT A SUITABLE CONCENTRATION RANGE BETWEEN ABOUT 0.01 PPM BY WEIGHT AND ABOUT 1000 PPM BY WEIGHT.THE IMPURITIES CAN BE ADDED BY THREE DIFFERENT METHODS. IN THE FIRST METHOD, A COPPER SEED LAYER IS FIRST DEPOSITED INTO A RECEPTACLE AND AN ION IMPLANTATION PROCESS IS CARRIED OUT ON THE SEED LAYER, WHICH IS FOLLOWED BY ELECTROPLATING COPPER INTO THE RECEPTACLE. IN THE SECOND METHOD, A COPPER SEED LAYER IS FIRST DEPOSITED INTO A RECEPTACLE, A COPPER COMPOSITION CONTAINING IMPURITIES IS THEN ELECTRODEPOSITED INTO THE RECEPTACLE AND THE ELECTRONIC STRUCTURE IS ANNEALED SO THAT IMPURITIES DIFFUSE INTO THE COPPER SEED LAYER. IN THE THIRD METHOD, A BARRIER LAYER (82, 94) IS FIRST DEPOSITED INTO A RECEPTACLE, DOPANT IONS ARE THEN IMPLANTED INTO THE BARRIER LAYER WITH A COPPER SEED LAYER (84, 96) SUBSEQUENTLY DEPOSITED ON TOP OF THE BARRIER LAYER. AN ANNEALING PROCESS FOR THE ELECTRONIC STRUCTURE IS THEN CARRIED OUT SUCH THAT DOPANT IONS DIFFUSE INTO THE COPPER SEED LAYER. THE PRESENT INVENTION METHOD MAY FURTHER INCLUDE THE STEP OF ION-IMPLANTING AT LEAST ONE ELEMENT INTO A SURFACE LAYER OF THE COPPER CONDUCTOR (90, 100) AFTER THE CONDUCTOR IS FIRST PLANARIZED. THE SURFACE LAYER MAY HAVE A THICKNESS BETWEEN ABOUT 30 A AND ABOUT 500 A. AT LEAST ONE ELEMENT MAY BE SELECTED FROM CO, AI, SN, IN, TI AND CR.FIG. 2