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    MICROSTRUCTURE MODIFICATION IN COPPER INTERCONNECT STRUCTURE
    2.
    发明申请
    MICROSTRUCTURE MODIFICATION IN COPPER INTERCONNECT STRUCTURE 审中-公开
    铜互连结构的显微组织变化

    公开(公告)号：WO2009101040A2

    公开(公告)日：2009-08-20

    申请号：PCT/EP2009051427

    申请日：2009-02-09

    Applicant: IBM ,  IBM UK ,  CABRAL JR CYRIL ,  RODBELL KENNETH PARKER ,  BAKER BRETT CAROLINE ,  HUANG QIANG

    Inventor： CABRAL JR CYRIL ,  RODBELL KENNETH PARKER ,  BAKER BRETT CAROLINE ,  HUANG QIANG

    IPC: H01L21/768 ,  H01L23/532

    CPC classification number: H01L21/76877 ,  H01L21/76873 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Cobalt is added to a copper seed layer, a copper plating layer, or a copper capping layer in order to modify the microstructure of copper lines and vias. The cobalt can be in the form of a copper-cobalt alloy or as a very thin cobalt layer. The grain boundaries configured in bamboo microstructure in the inventive metal interconnect structure shut down copper grain boundary diffusion. The composition of the metal interconnect structure after grain growth contains from about 1 ppm to about 10 % of cobalt in atomic concentration. Grain boundaries extend from a top surface of a copper-cobalt alloy line to a bottom surface of the copper-cobalt alloy line, and are separated from any other grain boundary by a distance greater than a width of the copper-cobalt alloy line.

    Abstract translation: 钴添加到铜种子层，铜镀层或铜覆盖层以改变铜线和过孔的微观结构。 钴可以是铜钴合金的形式或非常薄的钴层。 在本发明金属互连结构中的竹微结构中配置的晶界关闭了铜晶界扩散。 晶粒生长后的金属互连结构的组成包含约1ppm至约10％的原子浓度的钴。 晶界从铜钴合金线的上表面延伸到铜钴合金线的下表面，并且与任何其他晶界分开大于铜钴合金线的宽度的距离。

    On-chip radiation dosimeter
    9.
    发明专利
    On-chip radiation dosimeter 未知

    公开(公告)号：GB2494231A

    公开(公告)日：2013-03-06

    申请号：GB201208932

    申请日：2012-05-21

    Applicant: IBM

    Inventor： YAU JENG-BANG ,  GORDON MICHAEL ,  RODBELL KENNETH PARKER

    IPC: H01L31/18 ,  G01T1/02 ,  H01L31/112

    Abstract: An implantation mask 204 is formed on a SOI or bulk silicon substrate such that a first portion of the substrate is located under the implant mask and a second portion of the substrate is exposed to oxygen ion implantation 301, forming charge/hole traps 302 in a buried oxygen layer (BOX) 202 or in the bulk silicon layer only in the un-masked portion of the substrate. After the mask is removed, FETs formed on the first portion of the substrate may be CMOS devices. FETs formed on the second portion of the substrate exhibit enhanced radiation sensitivity on account of the enhanced BOX layer (Fig. 4; 401) and can function as an on-chip semiconductor dosimeter to monitor the radiation exposure history of other devices on the substrate. After the oxygen ion implantation step, the mask may be further patterned and a second ion implantation step may be performed to give an area within the first portion of the substrate which comprises a BOX layer with an intermediate density of hole traps (Fig. 6; 604) so that FETs with intermediate radiation sensitivity can be fabricated. Multiple dosimeters may be formed, and different filter layers can correspond to different radiation types, for example a cover formed over an on-chip FDSOI dosimeter can prevent the dosimeter from detecting alpha-particles, or a filter can attenuate low energy x-rays but pass high energy gamma rays.

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