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公开(公告)号：DE3483152D1
公开(公告)日：1990-10-11
申请号：DE3483152
申请日：1984-05-30
Applicant: IBM
Inventor： FISK DALE EDWARD , PEREIRA LAWRENCE WILLIAM , RADIN GEORGE
Abstract: An internal bus mechanism for implementation in a computing system characterized by having a limited number of primitive general function instructions provided for controlling all system operations. The architecture oftheinternal bus mechanism defines a bus instruction format which specifies the bus unit being requested, the operation being requested, and sufficient data to specify the operands necessary to perform the requested operations. Two basic classes of instructions are provided, one wherein the CPU waits until a requested operation is performed and the other wherein the CPU issues an instruction to a bus unit and proceeds to execute further instructions in parallel with the operation of the bus unit. If desired, various units of the memory hierarchy may be designated and operated as bus units. To further the philosophy of a primitive instruction set, the present architecture utilizes a small number of bus unit instructions to replace a large number of additional system instructions which would be necessary if the bus units were arch itected as part of the CPU itself. Hardware design and system protocols are disclosed and described for implementing these architectural objectives.
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公开(公告)号：DE3380749D1
公开(公告)日：1989-11-23
申请号：DE3380749
申请日：1983-06-29
Applicant: IBM
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公开(公告)号：BR8406533A
公开(公告)日：1985-10-15
申请号：BR8406533
申请日：1984-12-18
Applicant: IBM
Inventor： FISK DALE EDWARD , PEREIRA LAWRENCE WILLIAM , RADIN GEORGE
Abstract: An internal bus mechanism for implementation in a computing system characterized by having a limited number of primitive general function instructions provided for controlling all system operations. The architecture oftheinternal bus mechanism defines a bus instruction format which specifies the bus unit being requested, the operation being requested, and sufficient data to specify the operands necessary to perform the requested operations. Two basic classes of instructions are provided, one wherein the CPU waits until a requested operation is performed and the other wherein the CPU issues an instruction to a bus unit and proceeds to execute further instructions in parallel with the operation of the bus unit. If desired, various units of the memory hierarchy may be designated and operated as bus units. To further the philosophy of a primitive instruction set, the present architecture utilizes a small number of bus unit instructions to replace a large number of additional system instructions which would be necessary if the bus units were arch itected as part of the CPU itself. Hardware design and system protocols are disclosed and described for implementing these architectural objectives.
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公开(公告)号：DE2758139A1
公开(公告)日：1978-07-13
申请号：DE2758139
申请日：1977-12-27
Applicant: IBM
Inventor： PEREIRA LAWRENCE WILLIAM
Abstract: IMAGE DATA REMAPPING SYSTEM A system remaps image data generated by successive sweeps of the image by a single transducer element into a format for use by a print head assembly which requires the simultaneous application of plural modulating signals to a plurality of print elements thereon to effect printing of the image. Horizontal strips of the image data corresponding to the height of the arrangement of print elements within the head assembly are successively transferred from a page buffer which stores the image to a horizontal strip buffer, from which successive columns of each strip along the length thereof are transferred through a rotator for rearrangement into new groups of data oriented at right angles relative to the prior arrangement thereof for storage in a vertical strip buffer. From the vertical strip buffer the new groups of data are applied through deserializers to modulate the plural print elements in the form of ink jet nozzle as the head assembly undergoes successive sweeps across a printable medium.
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