-
公开(公告)号：US3892925A
公开(公告)日：1975-07-01
申请号：US47568274
申请日：1974-06-03
Applicant: IBM
Inventor： FISK DALE EDWARD , HOMAN MERLE EDWARD , MEILEY CHARLES LAURIE , REYNOLDS ZACK DWAYNE , WATKINS ROBERT VERNON , WIEDMER FRITZ S
CPC classification number: H04Q11/04
Abstract: A multiple of telephone or like communications signal transmission lines are interconnected in time division multiplex (TDM) mode by integrated semiconductor switching circuitry. Preferably, electronic solid state structure most suitable for embodying field effect transistors (FET) and like associated devices is arranged in modular chip components permitting extension to large numbers of transmission lines, as desired. Input or calling transmission line terminals are connected to node busses by FET switches in predetermined time sequence under control of a central processing unit. Preferably, a separate timing pulse train generating circuit is used for the switching operation. Output or called transmission line terminals are connected to the node busses in predetermined time sequence at which every calling line is sampled at least once each switching cycle. Signal bandwidth is adjustable by arranging the switching circuitry to sample a calling line one, two, or more times in each switching cycle. Conventional semiconductor structure inherently forms capacitors of substantial reactance between the node busses and points of reference potential. Circuitry is incorporated in the arrangement for discharging the capacitors prior to connecting the input signal lines to the node busses. The circuitry also incorporates FET switch elements arranged for isolating uncalled output terminals from the switching circuitry, and for short circuiting each pair of idle output terminals.
Abstract translation: 电话或类似通信信号传输线路的多个通过集成半导体开关电路以时分复用（TDM）模式相互连接。 优选地，根据需要，最适于体现场效应晶体管（FET）等相关器件的电子固态结构被布置在允许扩展到大量传输线的模块化芯片组件中。 在中央处理单元的控制下，输入或呼叫传输线路终端通过FET开关以预定的时间顺序连接到节点总线。 优选地，单独的定时脉冲串生成电路用于切换操作。 输出或称为传输线路终端以预定的时间顺序连接到节点总线，每个呼叫线路在每个切换周期至少采样一次。 信号带宽可通过安排开关电路在每个开关周期中对一个或两个或更多次的呼叫线路进行采样来调整。 常规的半导体结构固有地形成节点总线和参考点之间的实质电抗的电容器。 在将输入信号线连接到节点总线之前，将电路并入用于放电电容器的布置。 该电路还包括FET开关元件，用于将不需要的输出端子与开关电路隔离，并且用于短路每对空闲输出端子。
-
2.发明授权
公开(公告)号：US3890472A
公开(公告)日：1975-06-17
申请号：US47568374
申请日：1974-06-03
Applicant: IBM
Inventor： FISK DALE EDWARD , HOMAN MERLE EDWARD
CPC classification number: H04Q11/04 , H04B14/02 , H04J3/1676 , H04L5/22 , H04L25/49
Abstract: Bilevel or bistatic digital electric signals are transmitted directly through a time division multiplexing (TDM) switching component asynchronously of the TDM clocking pulse train. A pulse duration modulated (PDM) electric signal or like wave is converted to a pulse amplitude modulated (PAM) electric wave having amplitude and timing components indicating a predetermined relationship to the TDM sampling period. The input PDM wave is amplitude limited by conventional circuitry and phase relationship is indicated by a ramp wave generator or a digital counter with the slope of the ramp wave or the counting rate proportional to the sampling period. Other forms of analog-todigital converter circuitry may be substituted. The converted PAM electric wave is then passed through the switching component in conventional manner. Thereafter, the switched PAM electric wave is analyzed for reconstructing the original PDM electric signal wave. Complementary circuitry is preferably used for regenerating the signal. The upper limit on the data rate corresponds to one transition of the input electric signal to one time division sampling period of the TDM switching component.
Abstract translation: 双层或双基数字电信号通过与TDM时钟脉冲串异步的时分复用（TDM）切换组件直接发送。 将脉冲持续时间调制（PDM）电信号或类似波转换成具有指示与TDM采样周期的预定关系的幅度和定时分量的脉冲幅度调制（PAM）电波。 输入PDM波由常规电路限幅，相位关系由斜波发生器或具有斜波斜率或与采样周期成比例的计数速率的数字计数器指示。 可以替代其他形式的模数转换器电路。 转换的PAM电波然后以常规方式通过开关部件。 此后，分析了切换的PAM电波，以重构原始的PDM电信号波。 互补电路优选用于再生信号。 数据速率的上限对应于TDM切换组件的输入电信号与一个时分采样周期的一个转换。
-
公开(公告)号：AU3548884A
公开(公告)日：1985-07-04
申请号：AU3548884
申请日：1984-11-16
Applicant: IBM
Inventor： FISK DALE EDWARD , PERIERA LAWRENCE WILLIAM , RADIN GEORGE
Abstract: An internal bus mechanism for implementation in a computing system characterized by having a limited number of primitive general function instructions provided for controlling all system operations. The architecture oftheinternal bus mechanism defines a bus instruction format which specifies the bus unit being requested, the operation being requested, and sufficient data to specify the operands necessary to perform the requested operations. Two basic classes of instructions are provided, one wherein the CPU waits until a requested operation is performed and the other wherein the CPU issues an instruction to a bus unit and proceeds to execute further instructions in parallel with the operation of the bus unit. If desired, various units of the memory hierarchy may be designated and operated as bus units. To further the philosophy of a primitive instruction set, the present architecture utilizes a small number of bus unit instructions to replace a large number of additional system instructions which would be necessary if the bus units were arch itected as part of the CPU itself. Hardware design and system protocols are disclosed and described for implementing these architectural objectives.
-
公开(公告)号：DE3483152D1
公开(公告)日：1990-10-11
申请号：DE3483152
申请日：1984-05-30
Applicant: IBM
Inventor： FISK DALE EDWARD , PEREIRA LAWRENCE WILLIAM , RADIN GEORGE
Abstract: An internal bus mechanism for implementation in a computing system characterized by having a limited number of primitive general function instructions provided for controlling all system operations. The architecture oftheinternal bus mechanism defines a bus instruction format which specifies the bus unit being requested, the operation being requested, and sufficient data to specify the operands necessary to perform the requested operations. Two basic classes of instructions are provided, one wherein the CPU waits until a requested operation is performed and the other wherein the CPU issues an instruction to a bus unit and proceeds to execute further instructions in parallel with the operation of the bus unit. If desired, various units of the memory hierarchy may be designated and operated as bus units. To further the philosophy of a primitive instruction set, the present architecture utilizes a small number of bus unit instructions to replace a large number of additional system instructions which would be necessary if the bus units were arch itected as part of the CPU itself. Hardware design and system protocols are disclosed and described for implementing these architectural objectives.
-
公开(公告)号：DE3366762D1
公开(公告)日：1986-11-13
申请号：DE3366762
申请日：1983-10-21
Applicant: IBM
Inventor： FISK DALE EDWARD , GRIFFITH ROBERT LEROY , HOMAN MERLE EDWARD , RADIN GEORGE , RICHARDS WALDO
Abstract: If a predetermined field (Figure 3/27) within a source instruction indexes and accesses a body of control information from memory (Figure 2/5), and if control information (Figure 4) designates the field-to-field (register-to-register) mapping (Figure 6), then a skeleton target instruction (Figure 3/29; Figure 4) can be filled in by either selectively copying the fields of the source instruction or otherwise computing same. If the mapping is executed by an interposed independent processor then overlapping of such conversion enhances throughput, the independent processor converting multifield instructions for a CPU of a first kind to multifield instuctions for a CPU of a second kind without disrupting the logical flow or execution of either source ortarget instruction streams.
-
Patent Agency Ranking
-
公开(公告)号：AU574737B2
公开(公告)日：1988-07-14
申请号：AU3548884
申请日：1984-11-16
Applicant: IBM
Inventor： FISK DALE EDWARD , PERIERA LAWRENCE WILLIAM , RADIN GEORGE
Abstract: An internal bus mechanism for implementation in a computing system characterized by having a limited number of primitive general function instructions provided for controlling all system operations. The architecture oftheinternal bus mechanism defines a bus instruction format which specifies the bus unit being requested, the operation being requested, and sufficient data to specify the operands necessary to perform the requested operations. Two basic classes of instructions are provided, one wherein the CPU waits until a requested operation is performed and the other wherein the CPU issues an instruction to a bus unit and proceeds to execute further instructions in parallel with the operation of the bus unit. If desired, various units of the memory hierarchy may be designated and operated as bus units. To further the philosophy of a primitive instruction set, the present architecture utilizes a small number of bus unit instructions to replace a large number of additional system instructions which would be necessary if the bus units were arch itected as part of the CPU itself. Hardware design and system protocols are disclosed and described for implementing these architectural objectives.
-
公开(公告)号：BR8406533A
公开(公告)日：1985-10-15
申请号：BR8406533
申请日：1984-12-18
Applicant: IBM
Inventor： FISK DALE EDWARD , PEREIRA LAWRENCE WILLIAM , RADIN GEORGE
Abstract: An internal bus mechanism for implementation in a computing system characterized by having a limited number of primitive general function instructions provided for controlling all system operations. The architecture oftheinternal bus mechanism defines a bus instruction format which specifies the bus unit being requested, the operation being requested, and sufficient data to specify the operands necessary to perform the requested operations. Two basic classes of instructions are provided, one wherein the CPU waits until a requested operation is performed and the other wherein the CPU issues an instruction to a bus unit and proceeds to execute further instructions in parallel with the operation of the bus unit. If desired, various units of the memory hierarchy may be designated and operated as bus units. To further the philosophy of a primitive instruction set, the present architecture utilizes a small number of bus unit instructions to replace a large number of additional system instructions which would be necessary if the bus units were arch itected as part of the CPU itself. Hardware design and system protocols are disclosed and described for implementing these architectural objectives.
-
公开(公告)号：DE2559770A1
公开(公告)日：1977-11-03
申请号：DE2559770
申请日：1975-05-27
Applicant: IBM
Inventor： FISK DALE EDWARD , HOMAN MERLE EDWARD , MEILEY CHARLES LAURIE
Abstract: A multiple of telephone or like communications signal transmission lines are interconnected in time division multiplex (TDM) mode by integrated semiconductor switching circuitry. Preferably, electronic solid state structure most suitable for embodying field effect transistors (FET) and like associated devices is arranged in modular chip components permitting extension to large numbers of transmission lines, as desired. Input or calling transmission line terminals are connected to node busses by FET switches in predetermined time sequence under control of a central processing unit. Preferably, a separate timing pulse train generating circuit is used for the switching operation. Output or called transmission line terminals are connected to the node busses in predetermined time sequence at which every calling line is sampled at least once each switching cycle. Signal bandwidth is adjustable by arranging the switching circuitry to sample a calling line one, two, or more times in each switching cycle. Conventional semiconductor structure inherently forms capacitors of substantial reactance between the node busses and points of reference potential. Circuitry is incorporated in the arrangement for discharging the capacitors prior to connecting the input signal lines to the node busses. The circuitry also incorporates FET switch elements arranged for isolating uncalled output terminals from the switching circuitry, and for short circuiting each pair of idle output terminals.
-
公开(公告)号：DE2523398A1
公开(公告)日：1975-12-04
申请号：DE2523398
申请日：1975-05-27
Applicant: IBM
Inventor： FISK DALE EDWARD , HOMAN MERLE EDWARD , MEILEY CHARLES LAURIE , REYNOLDS ZACK DWAYNE , WATKINS ROBERT VERNON , WIEDMER FRITZ SIMON
Abstract: A multiple of telephone or like communications signal transmission lines are interconnected in time division multiplex (TDM) mode by integrated semiconductor switching circuitry. Preferably, electronic solid state structure most suitable for embodying field effect transistors (FET) and like associated devices is arranged in modular chip components permitting extension to large numbers of transmission lines, as desired. Input or calling transmission line terminals are connected to node busses by FET switches in predetermined time sequence under control of a central processing unit. Preferably, a separate timing pulse train generating circuit is used for the switching operation. Output or called transmission line terminals are connected to the node busses in predetermined time sequence at which every calling line is sampled at least once each switching cycle. Signal bandwidth is adjustable by arranging the switching circuitry to sample a calling line one, two, or more times in each switching cycle. Conventional semiconductor structure inherently forms capacitors of substantial reactance between the node busses and points of reference potential. Circuitry is incorporated in the arrangement for discharging the capacitors prior to connecting the input signal lines to the node busses. The circuitry also incorporates FET switch elements arranged for isolating uncalled output terminals from the switching circuitry, and for short circuiting each pair of idle output terminals.
-
-
-
-
-
-
-
-
-
Search Results
12
records
(took 0.019 seconds)
