公开(公告)号：EP0800216A3

公开(公告)日：1998-10-07

申请号：EP97301764

申请日：1997-03-17

Applicant: IBM

Inventor： PHAN NGHIA VAN ,  SHEETS II JOHN EDWARD

IPC: H01L29/78 ,  H01L29/423

CPC classification number: H01L29/4238

Abstract: A field effect transistor is provided which includes a substrate having an active region and an adjacent non-active region. A gate conductor having a first gate conductor cross-sectional area is provided proximate the active region of the substrate. An increased gate conductor cross-sectional area is provided at the intersection of the active region and the non-active region to provide parallel current paths in order to circumvent agglomeration defects formed at the intersection.

公开(公告)号：JP2003216414A

公开(公告)日：2003-07-31

申请号：JP2003004702

申请日：2003-01-10

Applicant: IBM

Inventor： FRIEND DAVID MICHAEL ,  LUICK DAVID ARNOLD ,  PHAN NGHIA VAN

IPC: G06F7/50 ,  G06F7/508

Abstract: PROBLEM TO BE SOLVED: To provide a device and a method performing a high-speed arithmetic operation including addition in a pipeline circuit. SOLUTION: This device is provided with a plurality of gates in one embodiment, and a critical path passing through a plurality of gates is three-gate lag in some embodiments. This device is provided with a logic first level receiving, at least, two binary numbers and producing multi-bit P, G, Z and K carry signals, a logic second level receiving the multi-bit P, G, Z and K carry signals and producing multi-bit section base carry signal, and a logic third level having a plurality of domino logic gates receiving the multi-bit section base carry signal and forming an addition bit using the multi-bit P, G, Z and K carry signals for producing a sum of the received binary numbers. COPYRIGHT: (C)2003,JPO

公开(公告)号：JPH1012865A

公开(公告)日：1998-01-16

申请号：JP7319597

申请日：1997-03-26

Applicant: IBM

Inventor： PHAN NGHIA VAN ,  SHEETS II JOHN EDWARD

IPC: H01L29/78 ,  H01L29/423

Abstract: PROBLEM TO BE SOLVED: To provide a gate conductor which is improved so that its sensitivity to agglomeration failure may be limited at the transistor edge. SOLUTION: A field effect transistor 10 is provided with a substrate having an active region 12 and inactive regions 15a and 15b adjacent thereto. A gate conductor 18 having a sectional region of a first gate conductor is formed near the active region 12 of the substrate. The expanded sectional region of the gate conductor is formed on the cross-section of the region 12 and regions 15a and 15b, and a parallel current path rounding an agglomeration 24 formed on the cross section is provided.

公开(公告)号：DE3478731D1

公开(公告)日：1989-07-20

申请号：DE3478731

申请日：1984-07-11

Applicant: IBM

Inventor： GAUDENZI GENE JOSEPH ,  NORSWORTHY JOHN PAUL ,  PHAN NGHIA VAN ,  REEDY DENNIS CONWAY

IPC: H03K5/02 ,  H03K17/04 ,  H03K17/60 ,  H03K17/615 ,  H03K19/088 ,  H03K19/092

Abstract: Power dissipation in an off-chip driver circuit is decreased by utilizing a selectively switched transistor to discharge the base of the output pull-down transistor, and by using a large resistance in the base current path for the first stage of the Darlington pull-up transistors. An additional transistor having a larger emitter area and coupled to a lower potential source is connected in parallel with the normal phase-splitter transistor to provide additional output current sinking capability, and a current mirror is connected to control the current through both the phase splitting transistor and the additional transistor to control the turn-on transition of the pull-down output transistor.