Vertical FET with reduced parasitic capacitance

    公开(公告)号:GB2577185B

    公开(公告)日:2020-11-04

    申请号:GB201915887

    申请日:2018-04-11

    Applicant: IBM

    Abstract: A method for reducing parasitic capacitance of a semiconductor structure is provided. The method includes forming a fin structure over a substrate, forming a first source/drain region between the fin structure and the substrate, forming first spacers adjacent the fin structure, forming second spacers adjacent the first source/drain region and recessing the first source/drain region in exposed areas. The method further includes forming a shallow trench isolation (STI) region within the exposed areas of the recessed first source/drain region, depositing a bottom spacer over the STI region, forming a metal gate stack over the bottom spacer, depositing a top spacer over the metal gate stack, cutting the metal gate stack, forming a second source/drain region over the fin structure, and forming contacts such the STI region extends a length between the metal gate stack and the first source/drain region.

    Vertical FET with reduced parasitic capacitance

    公开(公告)号:GB2577185A

    公开(公告)日:2020-03-18

    申请号:GB201915887

    申请日:2018-04-11

    Applicant: IBM

    Abstract: A method for reducing parasitic capacitance of a semiconductor structure includes forming a fin structure over a substrate, forming a first source/drain region between the fin structure and the substrate, forming first spacers adjacent the fin structure, forming second spacers adjacent the first source/drain region and recessing the first source/drain region in exposed areas. The method further includes forming a shallow trench isolation (STI) region within the exposed areas of the recessed first source/drain region, depositing a bottom spacer over the STI region, forming a metal gate stack over the bottom spacer, depositing a top spacer over the metal gate stack, cutting the metal gate stack, forming a second source/drain region over the fin structure, and forming contacts such the STI region extends a length between the metal gate stack and the first source/drain region.

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