公开(公告)号：GB2581893B

公开(公告)日：2022-04-13

申请号：GB202006464

申请日：2018-11-01

Applicant: IBM

Inventor： CHEN ZHANG ,  KANGGUO CHENG ,  TENKO YAMASHITA ,  XIN MIAO ,  WENYU XU

IPC: H01L29/78 ,  H01L21/033 ,  H01L21/308 ,  H01L29/06

Abstract: Techniques for increasing Weff VFET devices are provided. In one aspect, a method of forming a fin structure includes: depositing a hardmask onto a substrate; depositing a mandrel material onto the hardmask; patterning the mandrel material along a first direction to form first mandrels; forming first spacers alongside the first mandrels; forming second mandrels in between the first mandrels; pattering the first/second mandrels along a second direction perpendicular to the first direction; forming second spacers, perpendicular to the first spacers, alongside the first/second mandrels; selectively removing the first/second mandrels leaving behind a ladder-shaped pattern formed by the first/second spacers; transferring the ladder-shaped pattern to the hardmask and then to the substrate. A method of forming a VFET device, a VFET fin structure, and a VFET device are also provided.

公开(公告)号：GB2577185B

公开(公告)日：2020-11-04

申请号：GB201915887

申请日：2018-04-11

Applicant: IBM

Inventor： XIN MIAO ,  KANGGUO CHENG ,  CHEN ZHANG ,  WENYU XU ,  PHILIP JOSEPH OLDIGES

IPC: H01L29/78 ,  H01L29/66

Abstract: A method for reducing parasitic capacitance of a semiconductor structure is provided. The method includes forming a fin structure over a substrate, forming a first source/drain region between the fin structure and the substrate, forming first spacers adjacent the fin structure, forming second spacers adjacent the first source/drain region and recessing the first source/drain region in exposed areas. The method further includes forming a shallow trench isolation (STI) region within the exposed areas of the recessed first source/drain region, depositing a bottom spacer over the STI region, forming a metal gate stack over the bottom spacer, depositing a top spacer over the metal gate stack, cutting the metal gate stack, forming a second source/drain region over the fin structure, and forming contacts such the STI region extends a length between the metal gate stack and the first source/drain region.

公开(公告)号：GB2581893A

公开(公告)日：2020-09-02

申请号：GB202006464

申请日：2018-11-01

Applicant: IBM

Inventor： CHEN ZHANG ,  KANGGUO CHENG ,  TENKO YAMASHITA ,  XIN MIAO ,  WENYU XU

IPC: H01L29/78

Abstract: Techniques for increasing Weff VFET devices are provided. In one aspect, a method of forming a fin structure includes: depositing a hardmask onto a substrate; depositing a mandrel material onto the hardmask; patterning the mandrel material along a first direction to form first mandrels; forming first spacers alongside the first mandrels; forming second mandrels in between the first mandrels; pattering the first/second mandrels along a second direction perpendicular to the first direction; forming second spacers, perpendicular to the first spacers, alongside the first/second mandrels; selectively removing the first/second mandrels leaving behind a ladder-shaped pattern formed by the first/second spacers; transferring the ladder-shaped pattern to the hardmask and then to the substrate. A method of forming a VFET device, a VFET fin structure, and a VFET device are also provided.

公开(公告)号：GB2577185A

公开(公告)日：2020-03-18

申请号：GB201915887

申请日：2018-04-11

Applicant: IBM

Inventor： XIN MIAO ,  KANGGUO CHENG ,  CHEN ZHANG ,  WENYU XU ,  PHILIP JOSEPH OLDIGES

IPC: H01L29/78 ,  H01L29/66

Abstract: A method for reducing parasitic capacitance of a semiconductor structure includes forming a fin structure over a substrate, forming a first source/drain region between the fin structure and the substrate, forming first spacers adjacent the fin structure, forming second spacers adjacent the first source/drain region and recessing the first source/drain region in exposed areas. The method further includes forming a shallow trench isolation (STI) region within the exposed areas of the recessed first source/drain region, depositing a bottom spacer over the STI region, forming a metal gate stack over the bottom spacer, depositing a top spacer over the metal gate stack, cutting the metal gate stack, forming a second source/drain region over the fin structure, and forming contacts such the STI region extends a length between the metal gate stack and the first source/drain region.