公开(公告)号：PL165457B1

公开(公告)日：1994-12-30

申请号：PL28972191

申请日：1991-04-03

Applicant: IBM

Inventor： BLANER BARTHOLOMEW ,  VASSILIADIS STAMATIS ,  PHILLIPS JAMES E

IPC: G06F9/00 ,  G01N33/04 ,  G01N33/44 ,  G06F7/575 ,  G06F9/30 ,  G06F9/302 ,  G06F9/38

公开(公告)号：CA2039639C

公开(公告)日：1995-02-14

申请号：CA2039639

申请日：1991-04-03

Applicant: IBM

Inventor： VASSILIADIS STAMATIS ,  PHILLIPS JAMES E ,  BLANER BARTHOLOMEW

IPC: G06F9/00 ,  G01N33/04 ,  G01N33/44 ,  G06F7/575 ,  G06F9/30 ,  G06F9/302 ,  G06F9/38

Abstract: A multi-function ALU for use in digital data processing is described, which facilitates the execution of instructions in parallel, thereby increasing processor performance. The proposed apparatus reduces the instruction execution latency that results from data dependency hazards in a pipelined machine. This latency reduction is accomplished by collapsing the interlocks due to these hazards. The proposed apparatus achieves performance improvement while maintaining compatibility with previous implementations designed using an identical architecture.