公开(公告)号：BR8704624A

公开(公告)日：1988-04-26

申请号：BR8704624

申请日：1987-09-04

Applicant: IBM

Inventor： BOURKE DONALD G ,  CHISHOLM DOUGLAS R ,  FLOAT GREGORY D ,  KELLEY RICHARD A ,  LIU ROY Y ,  MALMQUIST CARL A ,  NELSON JOHN M ,  PERKINS CHARLES B JR ,  PLACE RICHARD L ,  SCHWERMER HARTMUT R ,  WILSON JOHN DAVID

IPC: G06F13/36 ,  G06F13/40 ,  G06F13/20

Abstract: In a data processing system, an input output bus unit (IOBU) is connected to one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous "handshaking" manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, and SC/IOIU, such as a unit operation, a storage operation, and a message acceptance operation.

公开(公告)号：CA1297994C

公开(公告)日：1992-03-24

申请号：CA544335

申请日：1987-08-12

Applicant: IBM

Inventor： BOURKE DONALL G ,  CHISHOLM DOUGLAS R ,  FLOAT GREGORY D ,  KELLEY RICHARD A ,  LIU ROY Y ,  MALMQUIST CARL A ,  NELSON JOHN M ,  PERKINS CHARLES B ,  PLACE RICHARD L ,  SCHWERMER HARTMUT R ,  WILSON JOHN D

IPC: G06F13/36 ,  G06F13/40

Abstract: In a data processing system, an input output bus unit (IOBU) is connected to one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous "handshaking" manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, and SC/IOIU, such as a unit operation, a storage operation, and a message acceptance operation. EN980633