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公开(公告)号：JPH10214142A
公开(公告)日：1998-08-11
申请号：JP32994397
申请日：1997-12-01
Applicant: IBM
Inventor： NEAL DANNY M , KELLEY RICHARD A
Abstract: PROBLEM TO BE SOLVED: To provide a PCI local bus architecture for supporting a high speed operation by using a 5V signal environment and a 5V PCI connector in a system having backward interchangeability with present architecture definition. SOLUTION: A PCI local bus 202 in a data processing system is operated with 50MHz by using a 5V environment having a 5V connector for an add-in board and a proper timing budget. Only a 5V add-in board can be used for a 50MHz adapter mounted on the bus. This bus has backward interchangeability with existing 33MHz PCI specification, and when a 33MHz adapter is mounted, this is operated with 33MHz, and when a 50MHz adapter or a 66MHz adapter using a general board or both are mounted, this is operated with 50MH.
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公开(公告)号：JP2001022686A
公开(公告)日：2001-01-26
申请号：JP2000172663
申请日：2000-06-08
Applicant: IBM
Inventor： KELLEY RICHARD A , NEAL DANNY MARVIN , THURBER STEVEN MARK , ADARUBAATOU GIRAAMO JENS
Abstract: PROBLEM TO BE SOLVED: To provide an improved method and an execution system by which a buffer can be more effectively used in the case of transferring information between devices connected in an information processing system. SOLUTION: In this information processing system, a system bridge circuit can execute or over commits a transaction request from a system device to information transfer exceeding the current capacity of a bridge circuit in order to receive requested information while returning it from an instructed target device such as system memory 1O9 or other system device.
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公开(公告)号：PL185922B1
公开(公告)日：2003-08-29
申请号：PL33300697
申请日：1997-09-30
Applicant: IBM
Inventor： GUTHRIE GUY L , NEAL DANNY M , KELLEY RICHARD A
IPC: G06F13/40
Abstract: A method and system for providing the ability to add or remove components of a data processing system without powering the system down ("Hot-plug"). The system includes an arbiter, residing within a Host Bridge, Control & Power logic, and a plurality of in-line switch modules coupled to a bus. Each of the in-line switch modules provide isolation for load(s) connected thereto. The Host Bridge in combination with the Control & Power Logic implement the Hot-plug operations such as ramping up and down of the power to a selected slot, and activating the appropriate in-line switches for communication from/to a load (target/controlling master).
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公开(公告)号：CA1297994C
公开(公告)日：1992-03-24
申请号：CA544335
申请日：1987-08-12
Applicant: IBM
Inventor： BOURKE DONALL G , CHISHOLM DOUGLAS R , FLOAT GREGORY D , KELLEY RICHARD A , LIU ROY Y , MALMQUIST CARL A , NELSON JOHN M , PERKINS CHARLES B , PLACE RICHARD L , SCHWERMER HARTMUT R , WILSON JOHN D
Abstract: In a data processing system, an input output bus unit (IOBU) is connected to one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous "handshaking" manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, and SC/IOIU, such as a unit operation, a storage operation, and a message acceptance operation. EN980633
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公开(公告)号：CA1315890C
公开(公告)日：1993-04-06
申请号：CA598603
申请日：1989-05-03
Applicant: IBM
Inventor： CHISHOLM DOUGLAS R , ISEMINGER ROBERT G , KELLEY RICHARD A , LEUNG WAN L , MOYER JAMES T , SNEDAKER MARK C
Abstract: In a computer system, a plurality of input/output processors (IOP's) are connected via an asynchronous input/output bus, called an "SPD" bus, to one side of an input/output interface controller (IOIC). The other side of the IOIC is connected to a storage controller (SC) via a synchronous bus called an "adapter" bus. The SC is connected to a common system memory and possibly also to an instruction processing unit. The SPD bus, which comprises three sub-buses and a control bus, conducts signals between each IOP and the IOIC in an asynchronous "handshaking" manner. The adapter bus, which comprises two sub-buses and a control bus, conducts signals between the IOIC and the SC in a synchronous manner. The IOIC, interconnected between the SPD bus and adapter bus, functions as a buffer between the faster synchronous bus and the slower asychronous bus. The IOIC also comprises at least one shared DMA facility for executing DMA storage operations requested by the IOP's via the SPD bus. Each shared DMA facility includes a buffer for control information and data to be transmitted between the SC and one of the IOP's and a bus interface coupled to the buffer, to the adapter bus and to the SPD bus for independently transferring the control information and data between the buffer and the SC, on one hand, via the adapter bus, and between the buffer and the one IOP, on the other hand, via the SPD bus. In this manner, the SPD bus can be released for utilization by other IOP's connected thereto during a period of "storage latency" after a DMA storage operation has been initiated by one IOP.
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Patent Agency Ranking
公开(公告)号：BR8704624A
公开(公告)日：1988-04-26
申请号：BR8704624
申请日：1987-09-04
Applicant: IBM
Inventor： BOURKE DONALD G , CHISHOLM DOUGLAS R , FLOAT GREGORY D , KELLEY RICHARD A , LIU ROY Y , MALMQUIST CARL A , NELSON JOHN M , PERKINS CHARLES B JR , PLACE RICHARD L , SCHWERMER HARTMUT R , WILSON JOHN DAVID
Abstract: In a data processing system, an input output bus unit (IOBU) is connected to one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous "handshaking" manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, and SC/IOIU, such as a unit operation, a storage operation, and a message acceptance operation.
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公开(公告)号：CA2273719C
公开(公告)日：2004-03-30
申请号：CA2273719
申请日：1999-06-04
Applicant: IBM
Inventor： FUHS RONALD E , BEUKEMA BRUCE L , THURBER STEVEN MARK , NEAL DANNY M , KELLEY RICHARD A
Abstract: A peripheral interconnect for a computer system comprising a bridge, a peripheral bus, and a peripheral device, wherein at least one of these components is adapted to selectively operate in either a high performance mode or a low performance mode, the high performance mode using a first operating speed and a first protocol, and the low performance mode using a second operating speed which is lower than said first operating speed, and a second protocol which is different from the first protocol. The disclosed embodiment provides a high performance mode with a 1 00 MHz speed and a protocol that disallows pacing, and a low performance mode that uses a 66 MHz or 33 MHz speed and a standard PCI protocol that allows pacing. The high performance operating speed can be twice the low performance operating speed, by doubling the clock frequency and clocking da ta on only one clock edge, or by clocking data on both a rising edge and a falling edge of a cloc k signal while operating at the lower clock frequency. High performance adapters can provide split transaction capability, with a high performance bridge having the ability to support split transactions o r alias split transactions to delayed transactions. Backward compatibility may also be provided for option al features such as hot-pluggability.
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公开(公告)号：CA2273719A1
公开(公告)日：2000-01-15
申请号：CA2273719
申请日：1999-06-04
Applicant: IBM
Inventor： BEUKEMA BRUCE L , THURBER STEVEN MARK , NEAL DANNY M , FUHS RONALD E , KELLEY RICHARD A
Abstract: A peripheral interconnect for a computer system comprising a bridge, a peripheral bus, and a peripheral device, wherein at least one of these components is adapted to selectively operate in either a high performance mode or a low performance mode, the high performance mode using a first operating speed and a first protocol, and the low performance mode using a second operating speed which is lower than said first operating speed, and a second protocol which is different from the first protocol. The disclosed embodiment provides a high performance mode with a 100 MHz speed and a protocol that disallows pacing, and a low performance mode that uses a 66 MHz or 33 MHz speed and a standard PCI protocol that allows pacing. The high performance operating speed can be twice the low performance operating speed, by doubling the clock frequency and clocking data on only one clock edge, or by clocking data on both a rising edge and a falling edge of a clock signal while operating at the lower clock frequency. High performance adapters can provide split transaction capability, with a high performance bridge having the ability to support split transactions or alias split transactions to delayed transactions. Backward compatibility may also be provided for optional features such as hot-pluggability.
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公开(公告)号：CA1199416A
公开(公告)日：1986-01-14
申请号：CA440692
申请日：1983-11-08
Applicant: IBM
Inventor： KELLEY RICHARD A , KURTZ HOBART L , MAGRISSO ISRAEL B , QUANSTROM JACK L
Abstract: An arbitration technique is described for use in conjunction with a parallel bus structure. Essentially, it involves the use of a Request signal instead of an Acknowledge signal as the propagated polling signal and making use of the delay elements in each bus unit, which act in parallel with poll propagation and with each other to reduce the net poll propagation time. Making use of the Request signal allows initiation of arbitration prior to the activation time of the Acknowledge line.
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公开(公告)号：BR8306942A
公开(公告)日：1984-07-24
申请号：BR8306942
申请日：1983-12-18
Applicant: IBM
Inventor： KELLEY RICHARD A , KURTZ HOBART L , MAGRISSO ISRAEL B , QUANSTROM JACK L
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