公开(公告)号：DE3168838D1

公开(公告)日：1985-03-28

申请号：DE3168838

申请日：1981-01-30

Applicant: IBM DEUTSCHLAND ,  IBM

Inventor： MIERSCH EKKEHARD DR ,  POLLMANN KURT ,  SCHETTLER HELMUT ,  ZUHLKE RAINER DR

IPC: H03F3/217 ,  H03F3/20 ,  H03F3/30 ,  H03K5/02 ,  H03K17/16 ,  H03K19/0175 ,  H03K19/088 ,  H03K6/02 ,  H03K19/003

Abstract: Push-pull driver with reduced noise generation resulting from driver switching. A further transistor is arranged between the driver output transistor (which becomes conductive at the low output level) and the chip ground line. Its base is connected to a reference voltage source the other pole of which is connected to the ground plane of the circuit card to which the corresponding semiconductor chip is attached. If a noise voltage is generated on the chip ground line, the emitter potential of the further transistor is pulled up. As its base potential is maintained at a fixed value by the applied reference potential, this transistor becomes less conductive. As a result, the rate of current change in the output stage is reduced. The slowed down current rise, leads to a reduced noise voltage developing on the common chip ground line. According to another embodiment of the invention the output transistor and said further transistor are combined to form one transistor whose base is maintained at a fixed voltage by means of two series-connected Schottky diodes.

公开(公告)号：BR8706324A

公开(公告)日：1988-07-19

申请号：BR8706324

申请日：1987-11-24

Applicant: IBM

Inventor： KLEIN KLAUS ,  POLLMANN KURT ,  SCHETTLER HELMUT ,  SCHULZ UWE ,  WAGNER OTTO M ,  ZUEHLKE RAINER

IPC: H01L21/82 ,  G06F17/50 ,  H01L21/822 ,  H01L27/04 ,  H01L21/92

Abstract: For the physical design of a VLSI chip a method is provided to implement a high density master image that contains logic and RAMs. In a hierarchical top-down design methodology the circuitry to be contained on the chip is logically devided into partitions that are manageable by the present automatic design systems and programs. Global wiring connection lines are from the beginning included into the design of the different individual partitions and treated there in the same way as circuits in that area. Thus the different partitions are designed in parallel. A floorplan is established that gives the different partitions a shape in such a way that they fit together without leaving any space between the different individual partitions. The chip need no extra space for global wiring and the partitions are immediataly attached to each other. The master image described is very flexible with respect to logic, RAM, ROM and other macros, and it offers some of the advantages of semicustom gate arrays and custom macro design. The thus designed chip shows no global wiring avenues between the partitions and has partitions of different porosity.

公开(公告)号：CA1275508C

公开(公告)日：1990-10-23

申请号：CA554556

申请日：1987-12-16

Applicant: IBM

Inventor： KLEIN KLAUS ,  POLLMANN KURT ,  SCHETTLER HELMUT ,  SCHULZ UWE ,  WAGNER OTTO M ,  ZUEHLKE RAINER

IPC: H01L21/82 ,  G06F17/50 ,  H01L21/822 ,  H01L27/04 ,  G06F15/60

Abstract: HIERARCHICAL TOP-DOWN METHOD FOR PHYSICAL VLSI-CHIP DESIGN For the physical design of a VLSI chip a method is provided to implement a high density master image that contains logic and RAMs. In a hierarchical top-down design methodology the circuitry to be contained on the chip is logically divided into partitions that are manageable by the present automatic design systems and programs. Global wiring connection lines are from the beginning included into the design of the different individual partitions and treated there in the same way as circuits in that area. Thus the different partitions are designed in parallel. A floor plan is established that gives the different partitions a shape in such a way that they fit together without leaving any space between the different individual partitions. The chip needs no extra space for global wiring and the partitions are immediately attached to each other. The master image described is very flexible with respect to logic, RAM, ROM and other macros, and it offers some of the advantages of semicustom gate arrays and custom macro design. The thus designed chip shows no global wiring avenues between the partitions and has partitions of different porosity.