公开(公告)号：US3927371A

公开(公告)日：1975-12-16

申请号：US44328474

申请日：1974-02-19

Applicant: IBM

Inventor： POMERANZ JEHOSHUA NAPHTALI ,  SCHNURMANN HENRI DANIEL

IPC: G01R31/319 ,  G06F11/26 ,  G01R15/12 ,  G01R31/30 ,  G06F11/00

CPC classification number: G01R31/31919 ,  G06F11/261

Abstract: A system for testing large scale integrated circuits. The circuitry in an integrated package such as a card, module or a semiconductor chip is viewed as a partially functional logic unit. This circuitry is complemented with off-package logic to allow the combination to act as a complete functional logic unit to which functional test patterns may be applied. The complementary logic is preferably simulated in the memory of a computer-controlled tester.

Abstract translation: 一种用于测试大规模集成电路的系统。 诸如卡，模块或半导体芯片的集成封装中的电路被视为部分功能逻辑单元。 该电路补充了非封装逻辑，以允许组合作为可应用功能测试模式的完整功能逻辑单元。 互补逻辑优选地在计算机控制的测试器的存储器中被模拟。

公开(公告)号：DE3781370D1

公开(公告)日：1992-10-01

申请号：DE3781370

申请日：1987-05-05

Applicant: IBM

Inventor： JACOBS SCOTT LAURENCE ,  NIHAL PERWAIZ ,  OZMAT BURHAN ,  SCHNURMANN HENRI DANIEL

IPC: H01L23/52 ,  H01L23/538 ,  H01L27/00

Abstract: A high speed, high performance integrated circuit packaging structure that may be used for emulating wafer scale integration structures. The preferred embodiment comprises an interposer (9) having a base substrate having alternating insulation and conductive layers thereon, wherein a plurality of the conductive layers are wiring means which are adapted for maintaining an extremely low noise level in the package. The low noise level and low resistance and capacitance of the wiring means allows a plurality of discrete semiconductor segments (32) to be mounted on and interconnected by the integrated circuit package with a significantly reduced number of drivers and receivers than required by Rent's Rule. Each integrated circuit structure (9) of the present invention emulates a large chip or wafer scale integration structure in performance without having to yield the large chip or wafer, and without redundancy schemes. A plurality of these integrated circuit packaging structures (9) are combined by decals (29, 31) to form a central processing unit (1) of a computer or a portion thereof. In an alternate preferred embodiment, the base substrate of the interposer is made of silicon and any required drivers are formed therein, thus substantially eliminating the need for any drivers on each of the discrete semiconductor segments (32).

公开(公告)号：DE68922695T2

公开(公告)日：1996-01-25

申请号：DE68922695

申请日：1989-10-24

Applicant: IBM

Inventor： HSIEH EDWARD PO-CHIU ,  MCMAHON MAURICE THOMAS ,  SCHNURMANN HENRI DANIEL

IPC: G01R31/317 ,  G01R31/3185 ,  G06F11/26 ,  G06F11/273 ,  G06F11/22

公开(公告)号：DE68922695D1

公开(公告)日：1995-06-22

申请号：DE68922695

申请日：1989-10-24

Applicant: IBM

Inventor： HSIEH EDWARD PO-CHIU ,  MCMAHON MAURICE THOMAS ,  SCHNURMANN HENRI DANIEL

IPC: G01R31/317 ,  G01R31/3185 ,  G06F11/26 ,  G06F11/273 ,  G06F11/22

公开(公告)号：DE3781370T2

公开(公告)日：1993-04-01

申请号：DE3781370

申请日：1987-05-05

Applicant: IBM

Inventor： JACOBS SCOTT LAURENCE ,  NIHAL PERWAIZ ,  OZMAT BURHAN ,  SCHNURMANN HENRI DANIEL

IPC: H01L23/52 ,  H01L23/538 ,  H01L27/00

Abstract: A high speed, high performance integrated circuit packaging structure that may be used for emulating wafer scale integration structures. The preferred embodiment comprises an interposer (9) having a base substrate having alternating insulation and conductive layers thereon, wherein a plurality of the conductive layers are wiring means which are adapted for maintaining an extremely low noise level in the package. The low noise level and low resistance and capacitance of the wiring means allows a plurality of discrete semiconductor segments (32) to be mounted on and interconnected by the integrated circuit package with a significantly reduced number of drivers and receivers than required by Rent's Rule. Each integrated circuit structure (9) of the present invention emulates a large chip or wafer scale integration structure in performance without having to yield the large chip or wafer, and without redundancy schemes. A plurality of these integrated circuit packaging structures (9) are combined by decals (29, 31) to form a central processing unit (1) of a computer or a portion thereof. In an alternate preferred embodiment, the base substrate of the interposer is made of silicon and any required drivers are formed therein, thus substantially eliminating the need for any drivers on each of the discrete semiconductor segments (32).

公开(公告)号：DE3065212D1

公开(公告)日：1983-11-10

申请号：DE3065212

申请日：1980-12-12

Applicant: IBM

Inventor： SCHNURMANN HENRI DANIEL

IPC: G01R31/28 ,  G01R31/319 ,  G06F11/26

Abstract: A method and apparatus for testing large or very large scale integrated circuit packages is described. The testing equipment required for testing such packages is assumed to lack the number of channels necessary to connect one channel to each input/output of the unit under test. A computer program classifies all input terminals in a plurality of categories, each of which corresponds to particular circuit type and electric network configuration connected to that pin. A unique set of DC levels is defined prior to testing for each class of inputs. These levels are supplied by the tester channels, each of which drives a multitude of input pins that belong to the same category. The assignment of tester channels in the aforementioned arrangement is implemented by means of multiplexers that select for each pin the appropriate set of DC levels, and a memory buffer contained in the tester, with the DC test patterns stored wherein. The bit configuration of each pattern controls plural switching devices that deliver the appropriate DC levels to the terminals of the unit.