公开(公告)号：JPH04180673A

公开(公告)日：1992-06-26

申请号：JP25546090

申请日：1990-09-27

Applicant: IBM

Inventor： SEIKI OGURA ,  POORU JIEI TSUANGU

IPC: H01L21/336 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/08 ,  H01L29/78

Abstract: PURPOSE: To easily manufacture a high capacity memory cell by injecting a P type impurity between a gate electrode and an insulation body area adjacent to it, performing reactive ion etching, then ion-injecting an N type impurity and forming a capacitor electrode. CONSTITUTION: After forming an SiO2 layer 14 around a polysilicon gate electrode, an insulation body layer 16 is formed. Then, the layer 16 is directionally reactively ion-etched and removed leaving a side wall spacer 20. Then, capacitor plate oxide is grown on an area 25, a blocking resist mask is applied and the P type impurity is injected. Then, the mask is removed and the N type impurity is injected and annealed. Then, polysilicon is stuck and a capacitor plate 30 is formed. Thus, the contour of less than 1μm is realized by using optical lithography and a fast dynamic RAM is easily manufactured.

公开(公告)号：JPH04118966A

公开(公告)日：1992-04-20

申请号：JP25545990

申请日：1990-09-27

Applicant: IBM

Inventor： SEIKI OGURA ,  POORU JIEI TSUANGU

IPC: H01L21/336 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/08 ,  H01L29/78

Abstract: PURPOSE: To manufacture a high-speed dynamic RAM using optical lithography by forming an N -type region by performing ion implantation of an N -type impurity before the ion implantation process of an N -impurity. CONSTITUTION: An insulator region 11 that extending toward the upper part of the surface of a body and is arranged with a gap is provided at the single- crystal silicon body. A polysilicon gate electrode 13 having basically a vertical surface is formed between adjacent insulator regions. An N -type impurity is subjected to ion implantation, and an N -type impurity region is formed between the vertical surface of the gate electrode and the insulator region. After that, by forming an insulator layer 16 at the top of the horizontal surface of the single-crystal silicon body, a nearly vertical surface is formed adjacently on a nearly horizontal surface. After that, finally insulator layer 16 formed is subjected to reaction ion etching, all of insulator layer 16 that is arranged nearly horizontally are eliminated, an insulator region with a narrow dimension being adjacent to a nearly vertical surface or a side wall spacer 20 is left, and an N -type impurity located at a lower side is protected from the later ion implantation of an N -type impurity.

公开(公告)号：JPS57157572A

公开(公告)日：1982-09-29

申请号：JP1651582

申请日：1982-02-05

Applicant: IBM

Inventor： BUEN WAI DOU ,  POORU JIEI TSUANGU

IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/336 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78

公开(公告)号：JPS57107070A

公开(公告)日：1982-07-03

申请号：JP14408181

申请日：1981-09-14

Applicant: IBM

Inventor： SEIKI OGURA ,  POORU JIEI TSUANGU

IPC: H01L21/336 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/08 ,  H01L29/78