公开(公告)号：DE3577022D1

公开(公告)日：1990-05-10

申请号：DE3577022

申请日：1985-11-19

Applicant: IBM

Inventor： CULICAN EDWARD FRANCIS ,  PRITZLAFF JR

IPC: H03K19/013 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04 ,  H01L27/118 ,  H03K19/003 ,  H03K19/088 ,  H03K19/173

Abstract: The invention is directed to integrated circuit chips and particularly to "gate array", or "master slices" whereon one or more circuits (IC1...IC5) drive a highly capacitive on-chip wiring (H, IC6) net. The driving circuits are modified and a compensation circuit (CC; R1, T1) coupled to the highly capacitive on-chip wiring net to mitigate the burden caused by the high capacitance. The integrated circuit structure contains, efficiently positioned on each chip, a number of compensation circuits which are readily connectable during the fabrication of the chip. The employment of one, or a number of, on-chip compensation circuits does not materially increase the chip power consumption.

公开(公告)号：DE3676620D1

公开(公告)日：1991-02-07

申请号：DE3676620

申请日：1986-10-07

Applicant: IBM

Inventor： CULICAN EDWARD FRANCIS ,  PRITZLAFF JR ,  VAN GOOR KENNETH ALAN ,  SCHETTLER HELMUT

IPC: H03K19/0175 ,  H03K17/60 ,  H03K19/013 ,  H03K19/018 ,  H03K19/088 ,  H03K19/082

Abstract: Circuitry for enhancing the ability of digital circuits to drive highly capacitive loads is disclosed. This circuitry has particular utility when employed with logic circuits such as "TTL" (Transistor- Transistor Logic) and "DTL" (Diode-Transistor Logic). … The circuitry (15) comprises four transistors (T1, T2, T3A, T3B) and two resistors (R1, R2), at least one of the transistors (T1, T3A) being connected as a diode.