公开(公告)号：GB2493057B

公开(公告)日：2015-02-18

申请号：GB201210965

申请日：2012-06-21

Applicant: IBM

Inventor： GERWIG GUENTER ,  LEHNERT FRANK ,  CREMER MICHAEL ,  PROBST PETER ROBERT

IPC: G06F9/38 ,  G06F9/26

公开(公告)号：GB2493057A

公开(公告)日：2013-01-23

申请号：GB201210965

申请日：2012-06-21

Applicant: IBM

Inventor： GERWIG GUENTER ,  LEHNERT FRANK ,  CREMER MICHAEL ,  PROBST PETER ROBERT

IPC: G06F9/38 ,  G06F9/26

Abstract: Instructions within an out of order execution processor are managed by receiving, at a recovery unit of the processor, an instruction that modifies a control register residing within the recovery unit (and thus the state of the processor). The recovery unit receives a first set of data associated with the instruction from a general register. A second set of data associated with the instruction is retrieved from the control register by the recovery unit. The recovery unit performs at least one binary logic operation on the first set of data and the second data. Wherein the data are addresses and tags relating to the received instruction and a currently execution instruction, and the binary logic operation performed is to check if the addresses match, and if they do, then compare the tags. The output of this compare operation can be used to prevent the current instruction from executing, or flush it from the pipeline. Further, the data resulting from performing the binary logic operation can be written to the control register, wherein the write queue is reordered. A shadow register can also be updated by the recovery unit over a common bus to hold a copy of the control register.