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    METHOD OF SHARING TRANSLATION LOOKASIDE BUFFER AMONG CPUS
    1.
    发明专利
    METHOD OF SHARING TRANSLATION LOOKASIDE BUFFER AMONG CPUS 审中-公开

    公开(公告)号：JP2002358235A

    公开(公告)日：2002-12-13

    申请号：JP2002115333

    申请日：2002-04-17

    Applicant: IBM

    Inventor： GAERTNER UTE ,  HAGSPIEL NORBERT ,  LEHNERT FRANK ,  PFEFFER ERWIN ,  SCHELM KERSTIN

    IPC: G06F12/1027 ,  G06F12/08 ,  G06F12/10

    Abstract: PROBLEM TO BE SOLVED: To provide a method and a system of sharing a TLB2 among CPUs transparently in the CPU architecture and therefore in compliance with the architecture rule. SOLUTION: This invention, in general, refers to a shared memory multiprocessor system of IBM ESA/390 or RS/6000 system, or the like, and in particular refers to the method and the system that share, among a plurality of CPUs, the translation lookaside buffer(TLB2) of second level to improve the performance and reduce a chip area necessary for buffering the result of virtual/absolute address translation. The invented TLB2 configuration includes a plurality of small arrays dedicated for a specific CPU, thus providing an interface for a main array shared among CPUs. The dedicated array is required to meet systematic restrictions and provide a link to a shared array commonly used by a plurality of CPUs.

    Handling an input/output store instruction
    3.
    发明专利
    Handling an input/output store instruction 未知

    公开(公告)号：AU2020213829A1

    公开(公告)日：2021-05-20

    申请号：AU2020213829

    申请日：2020-01-14

    Applicant: IBM

    Inventor： DRIEVER PETER ,  RAISCH CHRISTOPH ,  KRAEMER MARCO ,  LEHNERT FRANK ,  KLEIN MATTHIAS ,  BRADBURY JONATHAN ,  JACOBI CHRISTIAN ,  BELMAR BRENTON

    IPC: G06F9/30 ,  G06F13/20

    Abstract: A data processing system (210) and a method for handling an input/output store instruction (30), comprising a system nest (18) communicatively coupled to at least one input/output bus (22) by an input/output bus controller (20). The data processing system (210) further comprises at least a data processing unit (216) comprising a core (12), a system firmware (10) and an asynchronous core-nest interface (14). The data processing unit (216) is communicatively coupled to the system nest (18) via an aggregation buffer (16). The system nest (18) is configured to asynchronously load from and/or store data to at least one external device (214) which is communicatively coupled to the input/output bus (22). The data processing unit (216) is configured to complete the input/output store instruction (30) before an execution of the input/output store instruction (30) in the system nest (18) is completed. The asynchronous core-nest interface (14) comprises an input/output status array (44) with multiple input/output status buffers (24).

    Multiprocessor computer system
    7.
    发明专利
    Multiprocessor computer system 未知

    公开(公告)号：GB2529394A

    公开(公告)日：2016-02-24

    申请号：GB201414429

    申请日：2014-08-14

    Applicant: IBM

    Inventor： KOEHLER THOMAS ,  LEHNERT FRANK

    IPC: G06F12/10

    Abstract: An improved computer system (1) with multiple physical proces­sors (3) supports virtual addressing and shares main memory (5) and a translation lookaside buffer (TLB) (100) for virtual addressing. Virtual processors (3) are dispatched to the physical processors in time slice mode, the virtual proces­sors (3) represented by multiple execution threads, the logical state of all threads of a virtual processor (3) being stored in a state descriptor field in the main memory (5) when the virtual processor (3) is removed from one of the physical processors. Each thread has assigned a thread identifier unique to a virtual processor (3), each virtual processor (3) having an assigned unique state descriptor identifier. The TLB (100) comprises a first storing means (120) storing address transla­tions for the threads of the multiple virtual processors (3) un­der their respective thread identifier and state descriptor identifier; generation means (130) generating a sequence number when an entry in the TLB (100) is cre­ated; second storing means (120) responsive to the generation means (130) storing the sequence number together with a respec­tive thread identifier, state descriptor identifier, and a valid bit in a respective TLB entry, wherein the valid bit indicates if the TLB buffer en­try is valid or not; a state descriptor/thread array (110) stor­ing a dedicated valid bit and the sequence number for each thread identifier of each state descriptor identifier; and hit compare logic means to determine if an address translation is stored in the TLB (100) for a current thread identifier and a current state descriptor identifier by comparing the TLB entries with the en­tries in said state descriptor/thread array (110).

    Verfahren und Verarbeitungseinheit zur kontinuierlichen Bereitstellung eines Präzisionssystemakts
    8.
    发明专利
    Verfahren und Verarbeitungseinheit zur kontinuierlichen Bereitstellung eines Präzisionssystemakts 未知

    公开(公告)号：DE102012203531B4

    公开(公告)日：2016-02-11

    申请号：DE102012203531

    申请日：2012-03-06

    Applicant: IBM

    Inventor： GERWIG GÜNTER ,  VON BUTTLAR JOACHIM ,  LEHNERT FRANK ,  ENGLER EBERHARD ,  MEISSNER KLAUS

    IPC: G06F1/04

    Abstract: Die Erfindung betrifft ein Verfahren zur kontinuierlichen Bereitstellung eines Präzisionssystemtakts, der einem Prozessorkern (2) zugeordnet ist, wobei der Systemtakt ein Host-Taktregister (5) umfasst, das mithilfe eines Präzisionsoszillators aktualisiert wird, das Verfahren die Schritte des Bereitstellens eines Firmware-Taktregisters (6), des Hochzählens des Firmware-Taktregisters (6) bei jedem Hochzählen des Host-Taktregisters (5), der Überwachung von Ausfällen des Host-Taktregisters (5) und bei einem Ausfall des Host-Taktregisters (5) das kontinuierliche Hochzählen des Firmware-Taktregisters (6) mithilfe von Zeitsignalen des Prozessorkerns (2) sowie bei Empfang einer Anforderung auf Bereitstellung eines Taktwertes das Bereitstellen des Inhalts des Host-Taktregisters (5) umfasst, wenn kein Ausfall festgestellt wurde, und andernfalls den Inhalt des Firmware-Taktregisters (6).

    Out Of Order Processor with Millicode Instruction Control
    9.
    发明专利
    Out Of Order Processor with Millicode Instruction Control 未知

    公开(公告)号：GB2493057A

    公开(公告)日：2013-01-23

    申请号：GB201210965

    申请日：2012-06-21

    Applicant: IBM

    Inventor： GERWIG GUENTER ,  LEHNERT FRANK ,  CREMER MICHAEL ,  PROBST PETER ROBERT

    IPC: G06F9/38 ,  G06F9/26

    Abstract: Instructions within an out of order execution processor are managed by receiving, at a recovery unit of the processor, an instruction that modifies a control register residing within the recovery unit (and thus the state of the processor). The recovery unit receives a first set of data associated with the instruction from a general register. A second set of data associated with the instruction is retrieved from the control register by the recovery unit. The recovery unit performs at least one binary logic operation on the first set of data and the second data. Wherein the data are addresses and tags relating to the received instruction and a currently execution instruction, and the binary logic operation performed is to check if the addresses match, and if they do, then compare the tags. The output of this compare operation can be used to prevent the current instruction from executing, or flush it from the pipeline. Further, the data resulting from performing the binary logic operation can be written to the control register, wherein the write queue is reordered. A shadow register can also be updated by the recovery unit over a common bus to hold a copy of the control register.

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