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公开(公告)号：CA1163727A
公开(公告)日：1984-03-13
申请号：CA378333
申请日：1981-05-26
Applicant: IBM
Inventor： RAJEEVAKUMAR THEKKEMADATHIL V
IPC: H01L39/22 , H03K17/92 , H03K19/195
Abstract: YO980-055 SUPERCONDUCTING SOLITON DEVICES Josephson solitons are steered along selected paths in response to applied control signals, the output path chosen being dependent solely upon the presence and absence of these control signals. An input Josephson transmission line is provided along which the Josephson soliton travels. This input line intersects with two output Josephson transmission lines. Bias currents of opposite polarity in the output transmission lines are used to steer the soliton into a selected one of the output lines. At the intersection of the input line and the output lines an isolating resistor is located. This resistor dissipates the anti-soliton created at the intersection and provides isolation between the input and the output of the device. In a preferred embodiment, one electrode of the input and output Josephson transmission lines can be comprised of a common superconductor and the isolating resistor can be located between the other electrodes of the output transmission line. Path selection is determined solely by the control signal, and is not dependent upon internal damping of the device or the choice of boundary conditions at the intersections.
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公开(公告)号：CA1223352A
公开(公告)日：1987-06-23
申请号：CA485187
申请日：1985-06-25
Applicant: IBM
IPC: H03K19/096 , G11C8/10 , G11C11/34 , G11C11/407 , G11C11/413 , G06F12/02 , G11C7/00
Abstract: HIGH-PERFORMANCE, HIGH-DENSITY CMOS DECODER/DRIVER CIRCUIT A decoder/driver circuit for a semiconductor memory having A1 to AN (true) and ?? to ?? (complement) address lines for receiving A1 to AN address bit signals thereon from internal address buffers. A .PHI.PC line is included for receiving a .PHI.PC precharge clock signal thereon and a .PHI.R line is provided for receiving a .PHI.R reset clock signal thereon. The decoder/driver circuit includes a NOR decoder means having a plurality of transistor switching devices connected to A1 to AN-1 of ?? to ???? of the true and complement address lines for the AN to AN-1 address bits for producing a high or low level signal on a decoder output node depending on the address bits state. The decoder/driver circuit further includes a selection means having a plurality of transistor devices connected to the output node of the decoder to produce a first selection signal when the decoder output node and the AN line is high and a second selection signal when the decoder output node and the ?? line is high. A driver circuit is connected to the selection means and is responsive to the output signal of the NOR decoder circuit and the first selection signal to provide an output signal on a first memory word line and is further responsive to the output signal of the NOR decoder circuit and the second selection signal to provide an output signal on a second memory word line.
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公开(公告)号：CA1230422A
公开(公告)日：1987-12-15
申请号：CA485180
申请日：1985-06-25
Applicant: IBM
Inventor： RAJEEVAKUMAR THEKKEMADATHIL V , TERMAN LEWIS M
IPC: G11C11/407 , G11C7/12 , G11C7/22 , G11C8/08 , G11C8/18 , G11C11/409 , G11C11/41 , G11C7/00
Abstract: SELF-TIMED PRECHARGE CIRCUIT of the Invention A self-timed precharge circuit for a memory array consisting of an X-line complement means connected to the outputs of a plurality of falling edge detector means, and a precharge generator means connected to the output of the X-line complement means. Each falling edge detector means is connected to a separate wordline (WL, WL+1,...WL+N) of the system memory array. In operation, the precharge generator means is triggered with a signal on the output lead from a falling edge detector which is activated when the selected wordline (WL, WL+1,...WL+N) connected thereto resets.
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公开(公告)号：DE3165353D1
公开(公告)日：1984-09-13
申请号：DE3165353
申请日：1981-04-28
Applicant: IBM
Inventor： RAJEEVAKUMAR THEKKEMADATHIL V
IPC: H01L39/22 , H03K17/92 , H03K19/195
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