公开(公告)号：DE3681045D1

公开(公告)日：1991-10-02

申请号：DE3681045

申请日：1986-01-15

Applicant: IBM

Inventor： RAJEEVAKUMAR THEKKEMADATHIL VE ,  TERMAN LEWIS MADISON

IPC: G11C11/407 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/18 ,  G11C11/409 ,  G11C11/41 ,  G11C7/00

Abstract: A self-timed precharge circuit for a memory array consists of an X-line complement means (12) connected to the outputs (37) of a plurality of falling edge detector means (10), and a precharge generator means (14) connected to the output of the X-line complement means. Each falling edge detector means (10) is connected to a separate wordline of a system memory array. In operation, the precharge generator means (14) is triggered by a signal on the output lead (37) from a falling edge detector means (10) which is activated when the selected wordline connected theretoresets.

公开(公告)号：DE3685341D1

公开(公告)日：1992-06-25

申请号：DE3685341

申请日：1986-01-09

Applicant: IBM

Inventor： CHAPPELL BARBARA ALANE ,  RAJEEVAKUMAR THEKKEMADATHIL VE ,  SCHUSTER STANLEY EVERETT ,  TERMAN LEWIS MADISON

IPC: H03K19/096 ,  G11C8/10 ,  G11C11/34 ,  G11C11/407 ,  G11C11/413 ,  G11C8/00

Abstract: A decoder/driver circuit for a semiconductor memory having A1 to AN (true) and At to AN (complement) address lines for receiving A1 to AN address bit signals thereon from internal address buffers. A Ø PC line is included for receiving a Ø PC precharge clock signal thereon and a Ø R line is provided for receiving a 0 R reset clock signal thereon.The decoder/driver circuit includes a NOR decoder means having a plurality of transistor switching devices 41...44 connected to A1 to AN-1 orA1 toAN-1 of the true and complement address lines for the AN to AN-1 address bits for producing a high or low level signal on a decoder output node 1 4 depending on the address bits state. The decoder/driver circuit further includes a selection means having a plurality of transistor devices 24, 28 connected to the output node of the decoder to produce a first selection signal when the decoder output node and the AN line is high and a second selection signal when the decoder output node and the AN line is high. A driver circuit is connected to the selection means and is responsive to the output signal of the NOR decoder circuit and the first selection signal to provide an output signal on a first memory word line WLi and is further responsive to the output signal of the NOR decoder circuit and the second selection signal to provide an output sigraal on a second memory word line WLi + 1 .