公开(公告)号：GB2501997B

公开(公告)日：2014-03-26

申请号：GB201311046

申请日：2011-11-18

Applicant: IBM

Inventor： ARSOVSKI IGOR ,  PILO HAROLD ,  RAMADURAI VINOD

IPC: G11C7/12 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419

Abstract: A static random access memory (SRAM) write assist circuit with leakage suppression and level control is described. In one embodiment, the SRAM write assist circuit increases the amount of boost provided in a write cycle, while in another embodiment, the SRAM write assist circuit limits the amount of boost provided at higher supply voltages.

公开(公告)号：GB2501997A

公开(公告)日：2013-11-13

申请号：GB201311046

申请日：2011-11-18

Applicant: IBM

Inventor： ARSOVSKI IGOR ,  PILO HAROLD ,  RAMADURAI VINOD

IPC: G11C7/12 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419

Abstract: A static random access memory (SRAM) write assist circuit (400) with leakage suppression and level control is described. In one embodiment, the SRAM write assist circuit (400) increases the amount of boost provided in a write cycle, while in another embodiment, the SRAM write assist circuit (400) limits the amount of boost provided at higher supply voltages.