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    SYSTEM AND METHOD FOR EARLY WRITE TO MEMORY BY HOLDING BITLINE AT FIXED POTENTIAL
    1.
    发明公开
    SYSTEM AND METHOD FOR EARLY WRITE TO MEMORY BY HOLDING BITLINE AT FIXED POTENTIAL 有权
    系统和方法的早期著述IN MEMORY通过保持对公司潜在位线

    公开(公告)号：EP1433179A4

    公开(公告)日：2005-07-06

    申请号：EP01995491

    申请日：2001-12-10

    Applicant: IBM

    Inventor： BARTH JOHN E JR ,  PILO HAROLD

    IPC: G11C11/407 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/00

    CPC classification number: G11C7/22 ,  G11C7/12 ,  G11C2207/104

    Abstract: A system and method is disclosed for writing early within a memory cycle by holding only one of a true bitline (BTO) and a reference bitline (BC0) at a fixed potential, e.g. ground, when the sense amplifier (51) is set. The sense amplifier (51) amplifies a small voltage difference between the true bitline (BT0) and the reference bitline (BC0) to predetermined high and low voltage logic levels to write a datum to the memory cell. In this way, writing can complete in about the same time as reading, without risking corruption of data on adjacent bitlines in the memory. The bitlines are precharged to a fixed potential in a conduction path through the bitswitches (T1), rather than using local precharge devices at the sense amplifier (51). To write, bitswitches (T1) and writepath transistors (T3) apply the fixed potential to one of the true bitline (BT0) and the reference bitline (BC0). Bitswitches (T1) on such other memory cells not currently being written isolate the bitline coupled to those memory cells when setting the sense amplifiers, such that the stored contents of such memory cells not being written are refreshed (written back) at the time that the selected memory cell is written.

    Device and circuit for fine granularity power gating
    2.
    发明专利
    Device and circuit for fine granularity power gating 审中-公开
    精细电力供电的设备和电路

    公开(公告)号：JP2013122808A

    公开(公告)日：2013-06-20

    申请号：JP2012204695

    申请日：2012-09-18

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

    Inventor： PILO HAROLD ,  ROBERT MAURICE HOULE ,  STEVEN HALEY LAMPHIER

    IPC: G11C11/413

    CPC classification number: G11C11/413 ,  G11C8/08 ,  G11C8/10

    Abstract: PROBLEM TO BE SOLVED: To provide an approach for providing fine granularity power gating of a memory array.SOLUTION: In one embodiment, power supply lines are disposed in a horizontal dimension of the memory array parallel to the word lines that access cells arranged in rows and columns of the array, where each of the supply lines are shared by adjacent cells in the memory. Power supply lines that activate a row selected by one of the word lines are supplied with a full-power voltage value and power supply lines that activate rows adjacent to the selected row are supplied with a half-power voltage value, while the power supply lines of the remaining rows in the memory are supplied with a power-gated voltage value.

    Abstract translation: 要解决的问题：提供一种用于提供存储器阵列的精细粒度电源门控的方法。 解决方案：在一个实施例中，电源线被布置在存储器阵列的水平维度上，平行于访问以阵列的行和列排列的单元的字线，其中每个电源线由相邻单元共享 在记忆中 激活由字线之一选择的行的电源线被提供有全功率电压值，并且激活与所选行相邻的行的电源线被提供有半电源电压值，而电源线 的存储器中的剩余行被提供有电源门控电压值。 版权所有（C）2013，JPO＆INPIT

    SYSTEM AND METHOD FOR TESTING COLUMN REDUNDANCY OF INTEGRATED CIRCUIT MEMORY
    3.
    发明专利
    SYSTEM AND METHOD FOR TESTING COLUMN REDUNDANCY OF INTEGRATED CIRCUIT MEMORY 审中-公开

    公开(公告)号：JP2003196996A

    公开(公告)日：2003-07-11

    申请号：JP2002357703

    申请日：2002-12-10

    Applicant: IBM

    Inventor： PILO HAROLD

    IPC: G11C29/04 ,  G11C29/24 ,  G11C29/34 ,  G11C29/00

    Abstract: PROBLEM TO BE SOLVED: To provide a system and method for testing simultaneously a column of a semiconductor memory and a redundant column by adding temporarily an additional parallel signal bit giving wider band width during test mode operation to an input/output data bus connected to a semiconductor memory. SOLUTION: An input/output data bus has normally parallel signal bits of (n) pieces transmitting column data, but an additional parallel signal bit does not transmit normally column data and redundant column data. The additional parallel signal bit can transmit normally a clock signal such as an echo-clock or the like related to data outputted to a data bus. COPYRIGHT: (C)2003,JPO

    System and method for early write to memory by injecting small voltage signal
    4.
    发明专利
    System and method for early write to memory by injecting small voltage signal 有权
    通过注入小电压信号对存储器进行早期写入的系统和方法

    公开(公告)号：JP2003051189A

    公开(公告)日：2003-02-21

    申请号：JP2002176810

    申请日：2002-06-18

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

    Inventor： BARTH JR JOHN E ,  PILO HAROLD

    IPC: G11C11/409 ,  G11C7/06 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4094

    CPC classification number: G11C7/062 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4094

    Abstract: PROBLEM TO BE SOLVED: To perform a memory write operation in a short time being almost equal to the time for a read operation without destroying data on an adjacent bit line.
    SOLUTION: Before a sense amplifier is set, a small voltage difference signal is injected. Thereafter, by setting the sense amplifier, the sense amplifier amplifies the small voltage signal to prescribed high and low voltage logic levels for writing to the memory cell. Before the sense amplifier is set, local bit switches applies first and second write voltages having a small voltage difference to a true bit line and a reference bit line. Local bit switches on other bit lines are adapted so that a true bit line to be coupled to their memory cells and a reference bit line are separated before sense amplifiers to be coupled to their bit lines are set. Thereby, when a selected memory cell is written, the storage contents of a memory cell to which nothing is written is refreshed.
    COPYRIGHT: (C)2003,JPO

    Abstract translation: 要解决的问题：在不破坏相邻位线上的数据的情况下，在短时间内执行与读取操作的时间几乎相等的存储器写入操作。 解决方案：在设置读出放大器之前，注入一个小的电压差信号。 此后，通过设置读出放大器，读出放大器将小电压信号放大到规定的高电压和低电压逻辑电平以写入存储单元。 在设置读出放大器之前，局部位开关将具有小电压差的第一和第二写入电压施加到真位线和参考位线。 其他位线上的本地位开关被调整为使得要耦合到它们的存储器单元的真实位线和参考位线被分离，以便耦合到它们的位线的读出放大器被设置。 由此，当选择的存储单元被写入时，刷新没有写入的存储单元的存储内容。

    TRACKING CIRCUIT FOR PAIR OF DATA ECHO-CLOCK BEING INDEPENDENT OF CYCLE
    5.
    发明专利
    TRACKING CIRCUIT FOR PAIR OF DATA ECHO-CLOCK BEING INDEPENDENT OF CYCLE 失效

    公开(公告)号：JP2001167579A

    公开(公告)日：2001-06-22

    申请号：JP2000312408

    申请日：2000-10-12

    Applicant: IBM

    Inventor： PILO HAROLD ,  COVINO JAMES J

    IPC: G11C11/413 ,  G06F1/10 ,  G06F12/00 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407

    Abstract: PROBLEM TO BE SOLVED: To provide an echo-clock circuit securing accurate tracking of data transfer. SOLUTION: A comparator and a variable delay circuit are provided to keep tracking between data and echo-clock in a double data rate(DDR) RAM element. This is achieved by providing large region data signal (dummy data signal) tracking actual memory-array-data. This large region data signal is compared with a RAM clock, and a pipeline-clock (clock rise/clock fall) decides a delay time between the both to be de-layed. Conseauently, the pipeline-clock is pushed out as necessary so that it is transited after array data reaches an output latch. Therefore, when a cycle time is decreased, both of echo-clock and data are equally pushed out, and tracking re-quired for them is kept.

    FUNG
    7.
    发明专利
    FUNG 未知

    公开(公告)号：DE60228731D1

    公开(公告)日：2008-10-16

    申请号：DE60228731

    申请日：2002-07-11

    Applicant: IBM

    Inventor： NELSON ERIK A ,  PILO HAROLD

    IPC: G11C11/413 ,  G11C29/00 ,  G11C29/06 ,  G11C29/28 ,  G11C29/34

    Abstract: A method and structure for the invention includes an integrated memory structure having a built-in test portion. The integrated memory structure has memory cells, bitlines and wordlines connected to the memory cells, wordline decoders connected to a plurality of the wordlines, bitline restore devices connected to the bitlines for charging the bitlines during read and write operations, and a clock circuit connected to the wordlines. During a test mode the wordline decoders simultaneously select multiple wordlines that the bitline restore devices maintain in an active state and the clock circuit maintains th multiple wordlines and the bitline restore devices in an active state for a period in excess of a normal read cycle. The invention also includes transistors which are connected to the memory cells. The transistors include bitline contacts which are stressed during the test mode.

    SRAM-Verzögerungsschaltkreis, der die Charakteristiken von Bitzellen darstellt
    10.
    发明专利
    SRAM-Verzögerungsschaltkreis, der die Charakteristiken von Bitzellen darstellt 未知

    公开(公告)号：DE112010003722T5

    公开(公告)日：2013-01-10

    申请号：DE112010003722

    申请日：2010-09-08

    Applicant: IBM

    Inventor： ARSOVSKI IGOR ,  BRACERAS GEORGE M ,  HOULE ROBERT M ,  PILO HAROLD

    IPC: G11C11/41

    Abstract: Eine SRAM-Verzögerungsschaltung (14), die die Charakteristiken von Bitzellen darstellt. Eine Schaltung wird beschrieben, die enthält: einen Eingangsknoten zum Empfangen eines Eingangssignals (13); einen Referenzknoten (20) zum Aufnehmen eines Referenzstromes von einer Vielzahl von Referenzzellen (12); ein Netz von Kapazitäten (15) mit einer Entladung, die durch den Referenzstrom gesteuert wird; und eine Ausgangsschaltung, die das Eingangssignal mit einer Verzögerung (16) ausgibt, wobei die Verzögerung durch die Entladung des Netzes von Kapazitäten (15) gesteuert wird.

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