公开(公告)号：JP2004119970A

公开(公告)日：2004-04-15

申请号：JP2003305482

申请日：2003-08-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MISEWICH JAMES A ,  REOHR WILLIAM ROBERT ,  SCHROTT ALEJANDRO GABRIEL ,  RIIKON WAN

IPC: G11C11/22 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11502 ,  G11C11/22 ,  H01L21/28291 ,  H01L27/11507 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391

Abstract: PROBLEM TO BE SOLVED: To provide a ferroelectric gate field-effect tranisistor and a nonvolatile memory architecture, formed using it. SOLUTION: A vertical ferroelectric gate field-effect transistor (FeGFET) is provided with a substrate and a first drain/source electrode formed on the top surface of the substrate. A conductive channel region is formed on the top surface of the first drain/source electrode, and electrically connected to it. The FeGFET device is further provided with a ferroelectric gate region formed on at least one sidewall of the channel region, at least one gate electrode electrically contacting the ferroelectric gate region, and a second drain/source electrode, formed on the top surface of the channel region and electrically contacts the channel region. The ferroelectric gate region can be selectively polarized, depending on the potential supplied between the gate electrode and at least one of first and second drain/source electrode. A nonvolatile memory array, provided with a plurality of FeGFET device, is formed. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004118998A

公开(公告)日：2004-04-15

申请号：JP2003305497

申请日：2003-08-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： REOHR WILLIAM ROBERT ,  WANG LI-KONG

IPC: G11C11/22 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C11/22

Abstract: PROBLEM TO BE SOLVED: To provide an improved nonvolatile memory array provided with a plurality of memory cells. SOLUTION: At least one of the memory cells is provided with a three terminal nonvolatile storage element for memorizing the logical state of at least one memory cell. The memory array is provided with a plurality of writing lines operatively coupled to the memory cells for selectively writing the logical states of one or more memory cells in the memory array and a plurality of bit lines and word lines operatively coupled to the memory cells for selectively reading and writing the logical states of one or more memory cells in the memory array. The memory array is advantageously configured so as to eliminate the need for a pass gate being operatively coupled to a corresponding nonvolatile storage element in the at least one memory cell. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2005063414A

公开(公告)日：2005-03-10

申请号：JP2004203829

申请日：2004-07-09

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KNEBEL DANIEL R ,  REOHR WILLIAM ROBERT ,  WANG LI-KONG

IPC: G06F1/04 ,  G06F11/00 ,  G06F19/00

CPC classification number: G06F11/008

Abstract: PROBLEM TO BE SOLVED: To provide a frequency change technique that adjusts an operating frequency of an electronic system to compensate for one or more aging electronic components. SOLUTION: A number of performance parameters for an electronic system are determined at a particular age of the electronic system. The performance parameters can be correlated to a maximum operating frequency of electronic components of the electronic system for the particular age of the electronic system. The operating frequency of the electronic components is adjusted in accordance with the performance parameters. The performance parameters can include prior operating frequencies, hours of operation, ambient temperature, and supply voltage. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种调整电子系统的工作频率以补偿一个或多个老化的电子部件的频率变化技术。

解决方案：在电子系统的特定年龄确定电子系统的许多性能参数。 性能参数可以与电子系统的特定年龄的电子系统的电子部件的最大工作频率相关。 根据性能参数调整电子元件的工作频率。 性能参数可以包括以前的工作频率，工作时间，环境温度和电源电压。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2004055821A3

公开(公告)日：2004-11-04

申请号：PCT/EP0314011

申请日：2003-12-10

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： GOGL DIETMAR ,  SCHEUERLEIN ROY EDWIN ,  REOHR WILLIAM ROBERT

IPC: G11C11/16

CPC classification number: G11C11/1693 ,  G11C11/1673 ,  G11C11/1675

Abstract: A magnetic memory circuit comprises a plurality of memory cells and a plurality of bit lines coupled to the memory cells for selectively accessing one or more of the memory cells. The memory circuit comprises at least one bit line programming circuit, configurable as a current source for generating a programming current for writing a logical state of at least one memory cell and/or a current sink for returning the programming current, and a first set of switches. The first set of switches are disabled at least during a read operation of the memory cells and at least a portion of the first set of switches are selectively enabled during a write operation of the memory cells. Each switch in the first set of switches is configured to selectively couple the at least one bit line programming circuit to a corresponding one of the bit lines in response to a first control signal. The memory circuit further comprises at least one sense amplifier and a second set of switches. The second set of switches are disabled at least during a write operation of the memory cells and at least a portion of the second set of switches are selectively enabled during a read operation of the memory cells. Each switch in the second set of switches is configured to selectively couple the at least one sense amplifier to a corresponding one of the bit lines in response to a second control signal.

Abstract translation: 磁存储器电路包括多个存储器单元和耦合到存储器单元的多个位线，用于选择性地访问一个或多个存储器单元。 存储器电路包括至少一个位线编程电路，可配置为用于产生用于写入至少一个存储器单元的逻辑状态的编程电流的电流源和/或用于返回编程电流的电流吸收器，以及第一组 开关。 至少在存储器单元的读取操作期间禁用第一组开关，并且在存储器单元的写入操作期间选择性地使能第一组开关的至少一部分。 第一组开关中的每个开关被配置为响应于第一控制信号选择性地将至少一个位线编程电路耦合到对应的位线。 存储器电路还包括至少一个读出放大器和第二组开关。 至少在存储器单元的写入操作期间禁用第二组开关，并且在存储器单元的读取操作期间，第二组开关的至少一部分被选择性地使能。 第二组开关中的每个开关被配置为响应于第二控制信号选择性地将至少一个读出放大器耦合到对应的一个位线。

公开(公告)号：AU2003294886A8

公开(公告)日：2004-07-14

申请号：AU2003294886

申请日：2003-12-17

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DEBROSSE JOHN ,  GOGL DIETMAR ,  REOHR WILLIAM ROBERT

IPC: G11C7/06 ,  G11C7/18

Abstract: A symmetrical high-speed current sense amplifier having complementary reference cells and configurable load devices that eliminates architecture-related capacitive mismatch contributions. The current sense amplifier is adapted for use in a symmetric sensing architecture and includes a configurable load device. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal, the first clamping device being coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal, the second clamping device being coupled to the reference voltage. The load device may comprise a current mirror that is coupled between the first and second input of the voltage comparator. The current mirror may be configurable by select transistors. Alternatively, the load device may be a hard-wired current mirror, and a multiplexer may be used to select whether the first input signal or the second input signal is connected to a first or second side of the current mirror. Configurable dummy loads may be added at appropriate nodes to optimize the capacitive load and increase the speed of the amplifier. Equalization devices may be coupled between the first and second inputs of the voltage comparator, and between the first input signal and the second input signal.

公开(公告)号：AU2003293828A8

公开(公告)日：2004-07-09

申请号：AU2003293828

申请日：2003-12-10

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： GOGL DIETMAR ,  SCHEUERLEIN ROY EDWIN ,  REOHR WILLIAM ROBERT

IPC: G11C11/16

Abstract: A magnetic memory circuit comprises a plurality of memory cells and a plurality of bit lines coupled to the memory cells for selectively accessing one or more of the memory cells. The memory circuit comprises at least one bit line programming circuit, configurable as a current source for generating a programming current for writing a logical state of at least one memory cell and/or a current sink for returning the programming current, and a first set of switches. The first set of switches are disabled at least during a read operation of the memory cells and at least a portion of the first set of switches are selectively enabled during a write operation of the memory cells. Each switch in the first set of switches is configured to selectively couple the at least one bit line programming circuit to a corresponding one of the bit lines in response to a first control signal. The memory circuit further comprises at least one sense amplifier and a second set of switches. The second set of switches are disabled at least during a write operation of the memory cells and at least a portion of the second set of switches are selectively enabled during a read operation of the memory cells. Each switch in the second set of switches is configured to selectively couple the at least one sense amplifier to a corresponding one of the bit lines in response to a second control signal.

公开(公告)号：GB2511248A

公开(公告)日：2014-08-27

申请号：GB201410074

申请日：2012-11-23

Applicant: IBM

Inventor： REOHR WILLIAM ROBERT ,  MONTOYE ROBERT KEVIN ,  SPERLING MICHAEL

IPC: G11C11/406 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094

Abstract: A memory device includes one or more memory cells, each of the memory cells having corresponding bit and word lines connected thereto for individually accessing the memory cells, a word line circuit coupled with at least one word line, and a bit line circuit coupled with at least one bit line. The memory device further includes at least one control circuit coupled with the bit and word line circuits. The control circuit is operative, via the bit and word line circuits, and the bit and word lines, to cause state information to be stored in the memory cells. At least one switching element selectively connects the memory cells, the bit and word line circuits, and the control circuit to at least one power supply as a function of at least one control signal. The control circuit generates the control signal, in a data retention mode, for disconnecting at least portions of the word line and bit line circuits from the power supply while state information is retained in the memory cells.

公开(公告)号：DE60320301T2

公开(公告)日：2009-06-25

申请号：DE60320301

申请日：2003-12-10

Applicant: IBM ,  QIMONDA AG

Inventor： GOGL DIETMAR ,  SCHEUERLEIN ROY EDWIN ,  REOHR WILLIAM ROBERT

IPC: G11C11/16

Abstract: A magnetic memory circuit comprises a plurality of memory cells and a plurality of bit lines coupled to the memory cells for selectively accessing one or more of the memory cells. The memory circuit comprises at least one bit line programming circuit, configurable as a current source for generating a programming current for writing a logical state of at least one memory cell and/or a current sink for returning the programming current, and a first set of switches. The first set of switches are disabled at least during a read operation of the memory cells and at least a portion of the first set of switches are selectively enabled during a write operation of the memory cells. Each switch in the first set of switches is configured to selectively couple the at least one bit line programming circuit to a corresponding one of the bit lines in response to a first control signal. The memory circuit further comprises at least one sense amplifier and a second set of switches. The second set of switches are disabled at least during a write operation of the memory cells and at least a portion of the second set of switches are selectively enabled during a read operation of the memory cells. Each switch in the second set of switches is configured to selectively couple the at least one sense amplifier to a corresponding one of the bit lines in response to a second control signal.

公开(公告)号：DE112012004989B4

公开(公告)日：2016-11-03

申请号：DE112012004989

申请日：2012-11-23

Applicant: IBM

Inventor： MONTOYE ROBERT KEVIN ,  SPERLING MICHAEL ,  REOHR WILLIAM ROBERT

IPC: G11C11/34

Abstract: Speichereinheit, die aufweist: – eine Vielzahl von dynamischen Speicherzellen, wobei jede der Speicherzellen eine entsprechende Bit-Leitung und eine entsprechende Wortleitung aufweist, die damit verbunden sind, um individuell auf die Speicherzellen zuzugreifen; – eine Wortleitungsschaltung, die mit zumindest einer Wortleitung verbunden ist; – eine Bit-Leitungsschaltung, die mit zumindest einer Bit-Leitung verbunden ist; – zumindest eine Steuerschaltung, die mit der Bit- und Wortleitungsschaltung verbunden ist, zum Speichern über die Bit-Leitungsschaltung, die Wortleitungsschaltung und die Bit- und Wortleitung von Zustandsinformationen in den Speicherzellen; und – zumindest ein Schaltelement zum Verbinden der Speicherzellen, der Bit- und Wortleitungsschaltung und der Steuerschaltung selektiv mit zumindest einer Stromversorgung als Funktion zumindest eines Steuersignals; – wobei das zumindest eine Steuersignal zum Trennen von der Wortleitungs- und Bit-Leitungsschaltung von der Stromversorgung, während gleichzeitig Zustandsinformationen in den Speicherzellen aufbewahrt werden, und zum Wiederherstellen der Stromversorgung ausschließlich für die Wortleitungs- und Bit-Leitungsschaltung, die zum Durchführen einer Aktualisierung der Speicherzellen verwendet werden, dient, – wobei die Wortleitung in Abhängigkeit von einem PD-Steuersignal mit einer Versorgungsspannung (VWL) verbunden wird und sich das PD-Steuersignal – in einem Tiefschlafmodus auf einem Massepotential befindet und – im Betrieb auf einem hohen Logikpegel (VDD) oder alternativ auf einem niedrigen Logikpegel (VWL) befindet.

公开(公告)号：GB2511248B

公开(公告)日：2015-09-09

申请号：GB201410074

申请日：2012-11-23

Applicant: IBM

Inventor： REOHR WILLIAM ROBERT ,  MONTOYE ROBERT KEVIN ,  SPERLING MICHAEL

IPC: G11C11/406 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094