公开(公告)号：EP1208447A4

公开(公告)日：2004-10-20

申请号：EP00959157

申请日：2000-08-24

Applicant: IBM

Inventor： BASS BRIAN MITCHELL ,  CALVIGNAC JEAN LOUIS ,  HEDDES MARCO C ,  PATEL PIYUSH CHUNILAL ,  REVILLA JUAN GUILLERMO ,  SIEGEL MICHAEL STEVEN ,  VERPLANKEN FABRICE JEAN

IPC: G06F15/167 ,  G06F12/06 ,  G06F15/177 ,  H04L12/56 ,  H04Q11/04 ,  G06F15/16 ,  G06F12/00 ,  G06F13/16

CPC classification number: H04Q11/0478 ,  H04L2012/5681

Abstract: A network switch apparatus (10), components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a plurality of memory elements and a plurality of interface processors formed on a semiconductor substrate (10). The memory elements and interface processors together form a network processor (10) capable of cooperating with other elements in executing instructions directing the flow of data in a network. Access to the memory elements is controlled in a particular manner and under operative rules which provide controlled multiple accesses of the plurality of memory elements by a plurality of processors.

公开(公告)号：AT354830T

公开(公告)日：2007-03-15

申请号：AT00959157

申请日：2000-08-24

Applicant: IBM

Inventor： BASS BRIAN MITCHELL ,  CALVIGNAC JEAN LOUIS ,  HEDDES MARCO C ,  PATEL PIYUSH CHUNILAL ,  REVILLA JUAN GUILLERMO ,  SIEGEL MICHAEL STEVEN ,  VERPLANKEN FABRICE JEAN

IPC: G06F15/167 ,  G06F12/06 ,  G06F15/177 ,  H04L12/56 ,  H04Q11/04 ,  G06F15/16 ,  G06F12/00 ,  G06F13/16

Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a plurality of memory elements and a plurality of interface processors formed on a semiconductor substrate. The memory elements and interface processors together form a network processor capable of cooperating with other elements in executing instructions directing the flow of data in a network. Access to the memory elements is controlled in a particular manner and under operative rules which provide controlled multiple accesses of the plurality of memory elements by the plurality of processors.