公开(公告)号：JP2004171751A

公开(公告)日：2004-06-17

申请号：JP2003384262

申请日：2003-11-13

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ASANO HIDEO ,  HASSNER MARTIN AURELIANO ,  HEISE NYLES NORBERT ,  HETZLER STEVEN R ,  TAMURA TETSUYA

IPC: G06F11/10 ,  G06F11/00 ,  G11B5/09 ,  G11B20/18 ,  H03M13/00 ,  H03M13/03 ,  H03M13/11 ,  H03M13/15 ,  H03M13/29 ,  H03M13/47

CPC classification number: H03M13/25 ,  G06F11/1076 ,  G06F2211/104 ,  H03M13/1515 ,  H03M13/29 ,  H03M13/47

Abstract: PROBLEM TO BE SOLVED: To provide an encoding system and related method which prevent erroneous correction by parity sector correction in on-drive RAID system or the like.
SOLUTION: In this system, A parity cluster block being a perfect cluster itself receiving C3 protection is added. There is seldom possibility of providing defective data even if "jami" error is caused by providing such functions as C4 level correction of a cluster level by a parity sector checked and verified by C3 check having a high reliability level and checking compatibility of the cluster block. Scrub algorithm avoids read-out - change - write-in operation by delaying finish of C2 and C3 check until a storage device becomes an idle state.
COPYRIGHT: (C)2004,JPO

公开(公告)号：DE69023372D1

公开(公告)日：1995-12-14

申请号：DE69023372

申请日：1990-02-21

Applicant: IBM

Inventor： GALBRAITH RICHARD LEO ,  HEISE NYLES NORBERT

IPC: G06F3/06 ,  G11B20/10 ,  G11B20/12 ,  G11B20/18

公开(公告)号：DE3071860D1

公开(公告)日：1987-01-22

申请号：DE3071860

申请日：1980-12-12

Applicant: IBM

Inventor： LEWIS DAVID OTTO ,  PERTZBORN JAMES JOHN ,  ROBINSON THOMAS SCOTT ,  HEISE NYLES NORBERT ,  HOFFMAN ROY LOUIS ,  KISS ISTVAN STEVE

IPC: G06F13/12 ,  G06F12/10 ,  G06F13/10 ,  G06F13/18

Abstract: In virtual storage data processing apparatus including real main storage, 10 a virtual address translation unit VAT 15 and a common I/O control unit 110 serving plural I/O devices, 150 the virtual address translation unit includes a resolved address register for each I/O device, a pool of resolved address registers and control logic responsive to a device specific CPU I/O command for initiating chaines I/O data transfers to cause the VAT apparatus to translate a first virtual address to be used in the chained data transfer operation and load the translated (resolved) address the appropriate resolved address register and responsive to a command from the shared control unit indicating that one of the commanded I/O devices is ready for data transfer to become nonresponsive to further CPU I/O commands and cause the VAT to resolve a succession of virtual addresses for the data transfer and to load the resolved addresses into resolved address registers of the pool whereby a data transfer operation can commence using the resolved address in the register unique to the I/O device which is first ready for data transfer and thereafter continue with data transfers using resolved addresses from the registers shared by all of the I/O devices but captured for use by the I/O device first ready for data transfer. Upon the data transfers being completed for that I/O device, the VAT resolves a succession of virtual addresses and loads them into the shared registers for use during data transfers by the next ready I/O device in response to a command from the shared I/O control unit.

公开(公告)号：DE2312304A1

公开(公告)日：1973-10-25

申请号：DE2312304

申请日：1973-03-13

Applicant: IBM

Inventor： BROOKS EVERETT GERRISH ,  HEISE NYLES NORBERT ,  LEWIS DAVID OTTO ,  POOLER GLENN DAVID ,  ROCHESTER MINN ,  ZIMMERMAN DEAN OWEN

IPC: G06F13/10 ,  G06F13/24 ,  G06F3/04

公开(公告)号：MY134625A

公开(公告)日：2007-12-31

申请号：MYPI20034023

申请日：2003-10-22

Applicant: IBM

Inventor： ASANO HIDEO ,  HASSNER MARTIN AURELIANO ,  HEISE NYLES NORBERT ,  HETZLER STEVEN R ,  TAMURA TETSUYA

IPC: G06F11/10 ,  G11B5/09 ,  G06F11/00 ,  G11B20/18 ,  H03M13/00 ,  H03M13/03 ,  H03M13/11 ,  H03M13/15 ,  H03M13/29 ,  H03M13/47

Abstract: AN ENCODING SYSTEM AND ASSOCIATED METHOD PROTECT AGAINST MISCORRECTION DUE TO PARITY SECTOR CORRECTION IN, FOR EXAMPLE, AN ON-DRIVE RAID SYSTEM. THE SYSTEM ADDS A PARITY CLUSTER BLOCK, WHICH ITSELF IS A COMPLETE, C3-PROTECTED CLUSTER. HAVING THE CLUSTER LEVEL, C4 LEVEL CORRECTION, BY PARITY SECTORS, CHECKED AND VERIFIED BY C3 CHECKS THAT HAVE HIGH RELIABILITY LEVEL, AS WELL AS THE CAPABILITY FOR CHECKING CONSISTENCY OF A CLUSTER BLOCK, EVEN IN THE PRESENCE OF "JAMI" ERRORS, MAKES THIS POSSIBILITY UNLIKELY. A SCRUB ALGORITHM AVOIDS READ-MODIFY-WRITE OPERATIONS BY DEFERRING THE COMPLETION OF THE C2 AND C3-CKECKS UNTIL THE STORAGE DEVICE IS ADLE.(FIG 5)

公开(公告)号：DE69023372T2

公开(公告)日：1996-06-20

申请号：DE69023372

申请日：1990-02-21

Applicant: IBM

Inventor： GALBRAITH RICHARD LEO ,  HEISE NYLES NORBERT

IPC: G06F3/06 ,  G11B20/10 ,  G11B20/12 ,  G11B20/18

公开(公告)号：MX150980A

公开(公告)日：1984-09-03

申请号：MX18558581

申请日：1981-01-16

Applicant: IBM

Inventor： HEISE NYLES NORBERT ,  HOFFMAN ROY LOUIS ,  KISS ISTVAN STEVE ,  LEWIS DAVID OTTO ,  PERTZBORN JAMES JOHN ,  ROBINSON THOMAS-SCOTT

IPC: G06F13/12 ,  G06F12/10 ,  G06F13/10 ,  G06F13/18 ,  H04B1/00

Abstract: In virtual storage data processing apparatus including real main storage, 10 a virtual address translation unit VAT 15 and a common I/O control unit 110 serving plural I/O devices, 150 the virtual address translation unit includes a resolved address register for each I/O device, a pool of resolved address registers and control logic responsive to a device specific CPU I/O command for initiating chaines I/O data transfers to cause the VAT apparatus to translate a first virtual address to be used in the chained data transfer operation and load the translated (resolved) address the appropriate resolved address register and responsive to a command from the shared control unit indicating that one of the commanded I/O devices is ready for data transfer to become nonresponsive to further CPU I/O commands and cause the VAT to resolve a succession of virtual addresses for the data transfer and to load the resolved addresses into resolved address registers of the pool whereby a data transfer operation can commence using the resolved address in the register unique to the I/O device which is first ready for data transfer and thereafter continue with data transfers using resolved addresses from the registers shared by all of the I/O devices but captured for use by the I/O device first ready for data transfer. Upon the data transfers being completed for that I/O device, the VAT resolves a succession of virtual addresses and loads them into the shared registers for use during data transfers by the next ready I/O device in response to a command from the shared I/O control unit.