公开(公告)号：US3617914A

公开(公告)日：1971-11-02

申请号：US3617914D

申请日：1969-07-07

Applicant: IBM

Inventor： DORLER JACK A ,  ROBORTACCIO ROCCO

IPC: G05F1/56 ,  G05F3/22 ,  H03F1/32

CPC classification number: G05F3/22 ,  G05F3/225 ,  G05F3/227

Abstract: A monolithic circuit constant voltage source comprising an emitter-follower amplifier and having a compensating voltage amplifier connected thereto in feedback relationship.

公开(公告)号：CA894411A

公开(公告)日：1972-02-29

申请号：CA894411D

Applicant: IBM

Inventor： DORLER JACK A ,  ROBORTACCIO ROCCO

IPC: G05F3/22 ,  H03F1/32

公开(公告)号：DE2555439A1

公开(公告)日：1976-06-24

申请号：DE2555439

申请日：1975-12-10

Applicant: IBM

Inventor： CAVALIERE JOSEPH R ,  ROBORTACCIO ROCCO

IPC: G01R31/3185 ,  G11C29/32 ,  G11C29/48 ,  G11C29/00 ,  G01R31/28 ,  H01L27/04

Abstract: An LSI semiconductor device includes a memory array incorporating address, data and buffer registers, and associated combinatorial and/or sequential logic circuitry. The array is "embedded" in the sense that the memory array is not directly accessible, either in whole or in part, from the input and output terminals or pads of the device. To facilitate testing, means which bypass the associated logic circuitry are provided for scanning information directly into the address and data registers. The information so introduced is shifted through the register strings. The interconnections from the associated logic circuitry are inhibited during the testing mode while the information shifting means are inhibited during an operative mode. The information scanned into the registers may be scanned out to determine whether there is a defect or problem in the register strings. Output levels from the array are compared with an expected output.

公开(公告)号：FR2295530A1

公开(公告)日：1976-07-16

申请号：FR7533273

申请日：1975-10-20

Applicant: IBM

Inventor： CAVALIERE JOSEPH R ,  ROBORTACCIO ROCCO

IPC: G01R31/3185 ,  G11C29/32 ,  G11C29/48 ,  G11C29/00 ,  G11C5/02

Abstract: An LSI semiconductor device includes a memory array incorporating address, data and buffer registers, and associated combinatorial and/or sequential logic circuitry. The array is "embedded" in the sense that the memory array is not directly accessible, either in whole or in part, from the input and output terminals or pads of the device. To facilitate testing, means which bypass the associated logic circuitry are provided for scanning information directly into the address and data registers. The information so introduced is shifted through the register strings. The interconnections from the associated logic circuitry are inhibited during the testing mode while the information shifting means are inhibited during an operative mode. The information scanned into the registers may be scanned out to determine whether there is a defect or problem in the register strings. Output levels from the array are compared with an expected output.