公开(公告)号：US3505535A

公开(公告)日：1970-04-07

申请号：US3505535D

申请日：1967-01-03

Applicant: IBM

Inventor： CAVALIERE JOSEPH R

IPC: H03K19/013 ,  H03K19/086 ,  H03K19/12

CPC classification number: H03K19/086 ,  H03K19/013

公开(公告)号：CA859295A

公开(公告)日：1970-12-22

申请号：CA859295D

Applicant: IBM

Inventor： CAVALIERE JOSEPH R

公开(公告)号：FR2296307A1

公开(公告)日：1976-07-23

申请号：FR7534734

申请日：1975-11-07

Applicant: IBM

Inventor： CAVALIERE JOSEPH R ,  EARDLEY DAVID B

IPC: H03H1/00 ,  H03H11/52 ,  H03K3/3565 ,  H03K5/02 ,  H03K17/0416 ,  H03K19/017 ,  H04B3/18 ,  H03H11/00

Abstract: The complementary metal-oxide-semiconductor technology is used to produce an integrated circuit with a negative resistance characteristic under voltage application to a given circuit region. A metal-oxide-semiconductor transistor of a first channel type has its gate connected to the switching nodes and its source-drain path in series with a load to operating voltage source. A second such transistor of opposite channel type has its source-drain path connecting the switching node to the operating voltage source terminal, coupled to the load. This second transistor gate is connected to the junction point of the load and the first transistor. Thus the application of a voltage to a given region at the switching node the source-drain path of the second transistor becomes conductive.

公开(公告)号：DE2555439A1

公开(公告)日：1976-06-24

申请号：DE2555439

申请日：1975-12-10

Applicant: IBM

Inventor： CAVALIERE JOSEPH R ,  ROBORTACCIO ROCCO

IPC: G01R31/3185 ,  G11C29/32 ,  G11C29/48 ,  G11C29/00 ,  G01R31/28 ,  H01L27/04

Abstract: An LSI semiconductor device includes a memory array incorporating address, data and buffer registers, and associated combinatorial and/or sequential logic circuitry. The array is "embedded" in the sense that the memory array is not directly accessible, either in whole or in part, from the input and output terminals or pads of the device. To facilitate testing, means which bypass the associated logic circuitry are provided for scanning information directly into the address and data registers. The information so introduced is shifted through the register strings. The interconnections from the associated logic circuitry are inhibited during the testing mode while the information shifting means are inhibited during an operative mode. The information scanned into the registers may be scanned out to determine whether there is a defect or problem in the register strings. Output levels from the array are compared with an expected output.

公开(公告)号：CA2007410C

公开(公告)日：1995-01-17

申请号：CA2007410

申请日：1990-01-09

Applicant: IBM

Inventor： CAVALIERE JOSEPH R ,  CHAN ALAN K-J ,  MICHAIL MICHEL S

IPC: G11C8/16 ,  G11C11/411 ,  G11C11/40 ,  G11C11/407

Abstract: A semiconductor memory cell for selectively storing or outputting differential signals responsive to a SELECT signal supplied on a word line includes: a transistor pair having cross-coupled base-collector terminals and emitter terminals connected to a common reference potential; sensing means connected to each of the base-collector terminals in the transistor pair, each of the sensing means including (a) a first diode having a cathode connected to the base-collector terminal, (b) a second diode having an anode connected to the anode of the first diode and a cathode connected to the word line, and (c) means connected at the commonly connected anodes of the first and second diodes for amplifying the signal thereat; writing means connected to each of the transistors in the transistor pair, the writing means including a transistor having a base connected to the word line and a collector connected to the base-collector terminal; and means for supplying constant current to each of the base-collector terminals and to each of the commonly connected anodes of the first and second diodes. The memory cell permits read access or select while maintaining the voltages on the latch nodes stable.

公开(公告)号：FR2295530A1

公开(公告)日：1976-07-16

申请号：FR7533273

申请日：1975-10-20

Applicant: IBM

Inventor： CAVALIERE JOSEPH R ,  ROBORTACCIO ROCCO

IPC: G01R31/3185 ,  G11C29/32 ,  G11C29/48 ,  G11C29/00 ,  G11C5/02

Abstract: An LSI semiconductor device includes a memory array incorporating address, data and buffer registers, and associated combinatorial and/or sequential logic circuitry. The array is "embedded" in the sense that the memory array is not directly accessible, either in whole or in part, from the input and output terminals or pads of the device. To facilitate testing, means which bypass the associated logic circuitry are provided for scanning information directly into the address and data registers. The information so introduced is shifted through the register strings. The interconnections from the associated logic circuitry are inhibited during the testing mode while the information shifting means are inhibited during an operative mode. The information scanned into the registers may be scanned out to determine whether there is a defect or problem in the register strings. Output levels from the array are compared with an expected output.

公开(公告)号：DE2549308A1

公开(公告)日：1976-07-08

申请号：DE2549308

申请日：1975-11-04

Applicant: IBM

Inventor： GRUODIS ALGIRDAS J ,  CAVALIERE JOSEPH R ,  EARDLEY DAVID B

IPC: H03H1/00 ,  H03H11/52 ,  H03K3/3565 ,  H03K5/02 ,  H03K17/0416 ,  H03K19/017 ,  H04B3/18 ,  H01L23/56

Abstract: The complementary metal-oxide-semiconductor technology is used to produce an integrated circuit with a negative resistance characteristic under voltage application to a given circuit region. A metal-oxide-semiconductor transistor of a first channel type has its gate connected to the switching nodes and its source-drain path in series with a load to operating voltage source. A second such transistor of opposite channel type has its source-drain path connecting the switching node to the operating voltage source terminal, coupled to the load. This second transistor gate is connected to the junction point of the load and the first transistor. Thus the application of a voltage to a given region at the switching node the source-drain path of the second transistor becomes conductive.